PCI1450 datasheet(13/132 Pages) TI

13 / 132 page

PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

terminal functions (continued)

Table 7. PCI Interface Control

TERMINAL

I/O

FUNCTION

NAME

GFN NO.

GJG NO.

TYPE

FUNCTION

DEVSEL

V20

T18

I/O

PCI device select. The PCI1450 asserts DEVSEL to claim a PCI cycle as the target device.

As a PCI initiator on the bus, the PCI1450 monitors DEVSEL until a target responds. If no

target responds before timeout occurs, then the PCI1450 terminates the cycle with an initiator

abort.

FRAME

T19

R18

I/O

PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to

indicate that a bus transaction is beginning, and data transfers continue while this signal is

asserted. When FRAME is deasserted, the PCI bus transaction is in the final data phase.

GNT

J20

J14

PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1450 access to the PCI

bus after the current data transaction has completed. GNT may or may not follow a PCI bus

request, depending on the PCI bus parking algorithm.

GPIO2/LOCK

V19

I/O

PCI bus general-purpose I/O pins or PCI bus lock. GPIO2/LOCK can be configured as PCI

LOCK and used to gain exclusive access downstream. Since this functionality is not typically

used, a general-purpose I/O may be accessed through this terminal. GPIO2/LOCK defaults

to a general-purpose input and can be configured through the

GPIO2 control register.

IDSEL

N20

M18

Initialization device select. IDSEL selects the PCI1450 during configuration space accesses.

IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.

IRDY

T18

R19

I/O

PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data

phase of the transaction. A data phase is completed on a rising edge of PCLK where both

IRDY and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states

are inserted.

PERR

U18

I/O

PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity

does not match PAR when PERR is enabled through bit 6 of the

command register.

REQ

K17

K15

PCI bus request. REQ is asserted by the PCI1450 to request access to the PCI bus as an

initiator.

SERR

U19

PCI system error. SERR is an output that is pulsed from the PCI1450 when enabled through

the

command register, indicating a system error has occurred. The PCI1450 need not be the

target of the PCI cycle to assert this signal. When SERR is enabled in the

bridge control

CardBus interface.

STOP

T17

T19

I/O

PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current

PCI bus transaction. STOP is used for target disconnects and is commonly asserted by target

devices that do not support burst data transfers.

TRDY

U20

R16

I/O

PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data

phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY

and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted.

PCI1450 Datasheet(PDF) 13 Page - Texas Instruments

PCI1450 Datasheet(HTML) 13 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL