THS7001, THS7002

70-MHz PROGRAMMABLE-GAIN AMPLIFIERS

SLOS214B – OCTOBER 1998 – REVISED AUGUST 1999

19

POST OFFICE BOX 655303

APPLICATION INFORMATION

optimizing frequency response for the preamplifiers (continued)

small-signal response. This is why in a configuration with a gain of 5, a feedback resistor of 5.1 k

Ω with a gain

resistor of 1.2 k

Ω only shows a small peaking in the frequency response. The parallel resistance is less than

1 k

Ω. This value, in conjunction with a very small stray capacitance test PCB, forms a zero on the edge of the

amplifier’s natural frequency response. To eliminate this peaking, all that needs to be done is to reduce the

feedback and gain resistances. One other way to compensate for this stray capacitance is to add a small

capacitor in parallel with the feedback resistor. This helps to neutralize the effects of the stray capacitance. To

keep this zero out of the operating range, the stray capacitance and resistor value’s time constant must be kept

low. But, as can be seen in Figures 14 – 19, a value too low starts to reduce the bandwidth of the amplifier. Table

1 shows some recommended feedback resistors to be used with the THS7001 and THS7002 preamplifiers.

Table 2. Recommended Feedback Resistors

GAIN

Rf for VCC = ±15 V and ± 5 V

2

499

Ω

–1

499

Ω

5

1 k

Ω

PGA gain control

The PGA section of the THS7001 and THS7002 IC allows for digital control of the gain. There are three digital

control pins for each side of the PGA (AG0 – AG2, and BG0 – BG2). Standard TTL or CMOS Logic will control

these pins without any difficulties. The applied logic levels are referred to the DGND pins of the THS7002. The

gain functions are not latched and therefore always rely on the logic at these pins to maintain the correct gain

settings. A 3.3 k

Ω resistor to ground is usually applied at each input to ensure a fixed logic state. The gain control

acts like break-before-make SPDT switches. Because of this action, the PGA will go into an open-loop condition.

This may cause the output to behave unpredictably until the switches closes in less than 1.5

µs. Due to the

topology of this circuit, the controlling circuitry must be able to sink up to 2

µA of current when 0-V is applied

to the gain control pin. A simplified circuit diagram of the gain control circuitry is shown in Figure 55.

+VCC

To Internal

Bias Circuitry

Control

–VCC

DGND

Gain

Figure 55. Simplified PGA Gain Control