PI2122 datasheet(7/19 Pages) VICOR

7 / 19 page

Picor Corporation • picorpower.com

PI2122

Rev1.0

Page 7 of 19

without entering the OCT mode. The pin can be

grounded to provide a low duty cycle mode or pulled

to VC for lower gate current to drive highly capacitive

loads with resulting higher duty cycle mode under

the fault condition. In either case if the resulting

temperature rise of the MOSFET and controller

reach thermal shutdown the thermal time constant of

the package will set a low frequency burst like duty

cycle condition and protect the MOSFETs.

OV:

The Overvoltage (OV) input trip point can be

programmed through an external resistive divider to

monitor the input voltage.

The OV comparator

initiates a fault condition and pulls the FT

pin low

when OV rises above the Overvoltage Rising

Threshold. The PI2122 will turn the MOSFETs off if

the OV and the Forward Current conditions are both

true.

The low resistance redundant paths of an

Active ORing system tend to force all the input

sources to the same voltage making it difficult to

identify the noncompliant source. By ANDing OV

with

the

Forward

Current

Threshold

the

noncompliant source is identified and disconnected

from the system.

Over-Temperature Detection:

The internal Over-Temperature block monitors the

junction temperature of the controller. The Over-

Temperature threshold is set to 145

°C with -10°C of

hysteresis.

When the controller temperature

exceeds this threshold, the Over-Temperature circuit

turns the MOSFETs off and initiates a fault condition

and pulls the FT pin low. This function will protect

the MOSFETs from thermal runaway conditions.

Fault:

The fault circuit output is an open collector with 40μs

delay to prevent any false triggering. The FT pin

will be pulled low when any of the following faults

occurs:

Figure 4: OCT Off time vs. OCT capacitor value

•

Reverse Current

VC and Internal Voltage Regulator:

The PI2122 has a separate input (VC) that provides

power to the control circuitry and the internal gate

driver. An internal regulator clamps the VC voltage

to 15.5V.

•

Forward Over-Current “AND” clamp detector is

cleared

•

Forward Low Current “AND” clamp detector is

cleared

•

Over Temperature

For high side applications, the VC input should be

4V above the bus voltage to properly enhance the

internal N-channel MOSFET.

•

Input Under-Voltage

•

Input Over-Voltage “AND” nominal Forward

Current

The internal regulator circuit has a comparator to

monitor VC voltage and initiates a FAULT condition

when VC is lower than the VC Under-Voltage

Threshold.

•

VC pin Under-Voltage

The Forward Current fault condition occurs when the

MOSFETs gates are high but are not conducting a

significant level of forward current or may indicate

the MOSFETs are shorted either internally or

externally (VD1-D2 < 5mV).

UV:

The Under Voltage (UV) input trip point can be

programmed through an external resistive divider to

monitor the input voltage. When UV falls below the

Under-Voltage Falling Threshold, UV comparator

initiates a fault condition and pulls the FT pin low

and turns off the MOSFETs.

A gate voltage detector prevents FOC or FWD from

initiating a fault when the MOSFET is in an OFF

condition.

The gate to SN voltage has to reach sufficient

voltage to establish the Rds(on) condition before

these faults are detected.

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