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PI2122 Datasheet(PDF) 13 Page - Vicor Corporation |
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PI2122 Datasheet(HTML) 13 Page - Vicor Corporation |
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13 / 19 page ![]() Application Information: The PI2122 is designed to replace ORing diodes and load disconnect switchs in high current redundant power architectures. Replacing a traditional diode with a PI2122 will result in significant power dissipation reduction as well as board space reduction, efficiency improvement, input power source and output protection plus additional protection features. This section describes in detail the procedure to follow when designing with the PI2122 Active ORing solution. A design example is presented for Active ORing with load disconnect. Fault Indication: FT output pin is an open collector and should be pulled up to the logic voltage or to the controller VC via a resistor (10KΩ) Over-Current Timer: OCT Connect a capacitor, in the range of 1nF to 20nF to set the off time after over-current shutdown (see Figure 4). Short Circuit Detect: SCD Connect SCD pin to VC to avoid high inrush current into a capacitive load, or connect SCD to GND pin for fast turn on. The internal MOSFETs gate drive current has two levels based on the SCD voltage level. Auxiliary Power Supply (Vaux): Vaux is an independent power source required to supply power to the VC input. The Vaux voltage should be 4V higher than Vin (redundant power source output voltage) to fully enhance the internal MOSFETs. A bias resistor (Rbias) is required if the bias supply (Vaux) is higher than 15V. Rbias should be connected between the VC pin and Vaux to limit the current into the internal shunt regulator. Minimize the resistor value for low Vaux voltage levels to avoid a voltage drop that may reduce the VC voltage lower than required to drive the gate of the internal MOSFETs. Select the value of Rbias using the following equations: max min IC VC Vaux Rbias clamp − = Rbias maximum power dissipation: Rbias VC Vaux Pd clamp Rbias 2 max ) ( − = Where: min Vaux : Vaux minimum voltage max Vaux : Vaux maximum voltage Clamp VC : Controller clamp voltage, 15.5V max IC : Controller maximum bias current, use 4.2mA Example: Vaux 20V to 30V Ω = − = − = K mA V V IC VC Vaux Rbias clamp 07 . 1 2 . 4 5 . 15 20 max min mW K V V Rbias VC Vaux Pd clamp Rbias 196 07 . 1 ) 5 . 15 30 ( ) ( 2 2 max = Ω − = − = Internal N-Channel MOSFET BVdss: In an application when the MOSFETs are turned off due to a fault, the series parasitic elements in the circuit may contribute to the MOSFET being exposed to a voltage higher than its voltage rating. It is critical to follow best layout practice to minimize parasitic inductance in the PCB layout especially in the high current path. In Active ORing applications when one of the input power sources is shorted, a large reverse current is sourced from the circuit output through the MOSFETs. Depending on the output impedance of the system, the reverse current may reach over 60A in some conditions before the MOSFET is turned off. Such high current conditions will store energy even in a small parasitic element. For example: a 1nH parasitic inductance with 60A reverse current will generate 1.8µJ (½Li 2). When the MOSFETs are turned off, the stored energy will be released and produce a high negative voltage ringing at D1. At the same time the energy stored at D2 of the internal MOSFETs will be released and produce a voltage higher than the load voltage. This event will create a high voltage difference between the drain and source of the MOSFET. To reduce the magnitude of the ringing voltage, add a ceramic capacitor very close to D1 that can react to the voltage ringing frequency and another capacitor close to D2. Recommended values for the ceramic capacitors are 1µF; refer to C5 and C7 in Figure 24. Note: Since the two MOSFETs are connected in to back- to-back configuration, the maximum breakdown voltage is BVdss of one MOSFET plus one diode forward voltage . OV and UV resistor selection: The UV and OV comparator inputs are used to monitor the input voltage and will indicate a fault condition when this voltage is out of range. The UV and OV pins can be configured in two different ways, either with a divider on each pin, or with a three- resistor divider to the same node, enabling the Picor Corporation • picorpower.com PI2122 Rev1.0 Page 13 of 19 |
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