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AD9231

Rev. 0 | Page 26 of 36

The AD9231 is placed in power-down mode either by the SPI

port or by asserting the PDWN pin high. In this state, the ADC

typically dissipates 2.2 mW. During power-down, the output

drivers are placed in a high impedance state. Asserting the

PDWN pin low returns the AD9231 to its normal operating

mode. Note that PDWN is referenced to the digital output

driver supply (DRVDD) and should not exceed that supply

voltage.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering power-

down mode and then must be recharged when returning to normal

operation. As a result, wake-up time is related to the time spent

in power-down mode, and shorter power-down cycles result in

proportionally shorter wake-up times.

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required. See the Memory Map section

for more details.

DIGITAL OUTPUTS

The AD9231 output drivers can be configured to interface with

1.8 V to 3.3 V CMOS logic families. Output data can also be

multiplexed onto a single output bus to reduce the total number

of traces required.

The CMOS output drivers are sized to provide sufficient output

current to drive a wide variety of logic families. However, large

drive currents tend to cause current glitches on the supplies

and may affect converter performance.

Applications requiring the ADC to drive large capacitive loads

or large fanouts may require external buffers or latches.

The output data format can be selected to be either offset binary

or twos complement by setting the SCLK/DFS pin when operating

in the external pin mode (see Table 11).

As detailed in the AN-877 Application Note, Interfacing to High

Speed ADCs via SPI, the data format can be selected for offset

binary, twos complement, or gray code when using the SPI control.

Table 11. SCLK/DFS Mode Selection (External Pin Mode)

Voltage at Pin

SCLK/DFS

SDIO/DCS

AGND

Offset binary (default)

DCS disabled(default)

DRVDD

Twos complement

DCS enabled

Digital Output Enable Function (OEB)

The AD9231 has a flexible three-state ability for the digital

output pins. The three-state mode is enabled using the OEB pin

or through the SPI interface. If the OEB pin is low, the output

data drivers and DCOs are enabled. If the OEB pin is high, the

output data drivers and DCOs are placed in a high impedance

state. This OEB function is not intended for rapid access to the

data bus. Note that OEB is referenced to the digital output

driver supply (DRVDD) and should not exceed that supply

voltage.

When using the SPI interface, the data outputs and DCO of

each channel can be independently three-stated by using the

output disable (OEB) bit (Bit 4) in Register 0x14.

TIMING

The AD9231 provides latched data with a pipeline delay of

9 clock cycles. Data outputs are available one propagation

delay (tPD) after the rising edge of the clock signal.

Minimize the length of the output data lines and loads placed

on them to reduce transients within the AD9231. These

transients can degrade converter dynamic performance.

The lowest typical conversion rate of the AD9231 is 3 MSPS. At

clock rates below 3 MSPS, dynamic performance can degrade.

Data Clock Output (DCO)

The AD9231 provides two data clock output (DCO) signals

intended for capturing the data in an external register. The CMOS

data outputs are valid on the rising edge of DCO, unless the DCO

clock polarity has been changed via the SPI. See Figure 2 and

Figure 3 for a graphical timing description.

Table 12. Output Data Format

Input (V)

Condition (V)

Offset Binary Output Mode

Twos Complement Mode

VIN+ − VIN−

< −VREF − 0.5 LSB

0000 0000 0000

1000 0000 0000

VIN+ − VIN−

= −VREF

0000 0000 0000

1000 0000 0000

VIN+ − VIN−

= 0

1000 0000 0000

0000 0000 0000

VIN+ − VIN−

= +VREF − 1.0 LSB

1111 1111 1111

0111 1111 1111

VIN+ − VIN−

> +VREF − 0.5 LSB

1111 1111 1111

0111 1111 1111

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