AD9231 datasheet(27/36 Pages) AD

27 / 36 page

AD9231

Rev. 0 | Page 27 of 36

BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

The AD9231 includes a built-in self-test feature designed to

enable verification of the integrity of each channel as well as to

facilitate board level debugging. A built-in self-test (BIST) feature

that verifies the integrity of the digital datapath of the AD9231

is included. Various output test options are also provided to place

predictable values on the outputs of the AD9231.

BUILT-IN SELF-TEST (BIST)

The BIST is a thorough test of the digital portion of the selected

AD9231 signal path. Perform the BIST test after a reset to ensure

the part is in a known state. During BIST, data from an internal

pseudorandom noise (PN) source is driven through the digital

datapath of both channels, starting at the ADC block output.

At the datapath output, CRC logic calculates a signature from

the data. The BIST sequence runs for 512 cycles and then stops.

Once completed, the BIST compares the signature results with a

pre-determined value. If the signatures match, the BIST sets Bit 0

of Register 0x24, signifying the test passed. If the BIST test failed,

Bit 0 of Register 0x24 is cleared. The outputs are connected

during this test, so the PN sequence can be observed as it runs.

Writing the value 0x05 to Register 0x0E runs the BIST. This enables

the Bit 0 (BIST enable) of Register 0x0E and resets the PN sequence

generator, Bit 2 (BIST INIT) of Register 0x0E. At the completion of

the BIST, Bit 0 of Register 0x24 is automatically cleared. The PN

sequence can be continued from its last value by writing a 0 in

Bit 2 of Register 0x0E. However, if the PN sequence is not reset,

the signature calculation does not equal the predetermined

value at the end of the test. At that point, the user needs to rely

on verifying the output data.

OUTPUT TEST MODES

The output test options are described in Table 16 at Address

0x0D. When an output test mode is enabled, the analog section

of the ADC is disconnected from the digital back-end blocks

and the test pattern is run through the output formatting block.

Some of the test patterns are subject to output formatting, and

some are not. The PN generators from the PN sequence tests

can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These

tests can be performed with or without an analog signal (if

present, the analog signal is ignored), but they do require

an encode clock. For more information, see the AN-877

Application Note, Interfacing to High Speed ADCs via SPI.

AD9231 Datasheet(PDF) 27 Page - Analog Devices

AD9231 Datasheet(HTML) 27 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL