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DM9010EP Datasheet(PDF) 38 Page - Davicom Semiconductor, Inc. |
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DM9010EP Datasheet(HTML) 38 Page - Davicom Semiconductor, Inc. |
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38 / 62 page ![]() DM9010 Single Chip Ethernet Controller with General Processor Interface Preliminary 38 Version: DM9010-17--DS-P04 Jan. 18, 2006 PDF = 0: No fault detected via parallel detection function 6.3 LP_NP_ABL E 0, RO Link Partner Next Page Able LP_NP_ABLE = 1: Link partner, next page available LP_NP_ABLE = 0: Link partner, no next page 6.2 NP_ABLE 0,RO/P Local Device Next Page Able NP_ABLE = 1: DM9010, next page available NP_ABLE = 0: DM9010, no next page DM9010 does not support this function, so this bit is always 0 6.1 PAGE_RX 0, RO/LH New Page Received A new link code word page received. This bit will be automatically cleared when the register (register 6) is read by management 6.0 LP_AN_ABL E 0, RO Link Partner Auto-negotiation Able A “1” in this bit indicates that the link partner supports Auto-negotiation 8.8 DAVICOM Specified Configuration Register (DSCR) - 16 Bit Bit Name Default Description 16.15 BP_4B5B 0,RW Bypass 4B5B Encoding and 5B4B Decoding 1 = 4B5B encoder and 5B4B decoder function bypassed 0 = Normal 4B5B and 5B4B operation 16.14 BP_SCR 0, RW Bypass Scrambler/Descrambler Function 1 = Scrambler and descrambler function bypassed 0 = Normal scrambler and descrambler operation 16.13 BP_ALIGN 0, RW Bypass Symbol Alignment Function 1 = Receive functions (descrambler, symbol alignment and symbol decoding functions) bypassed. Transmit functions (symbol encoder and scrambler) bypassed 0 = Normal operation 16.12 BP_ADPOK 0, RW BYPASS ADPOK Force signal detector (SD) active. This register is for debug only, not release to customer 1=Forced SD is OK, 0=Normal operation 16.11 Reserved RW Reserved Force to 0 in application 16.10 TX 1, RW 100BASE-TX Mode Control 1 = 100BASE-TX operation 16.9 Reserved 0, RO Reserved 16.8 Reserved 0, RW Reserved Force to 0 in application. |
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