DM9010EP datasheet(14/62 Pages) DAVICOM

14 / 62 page

DM9010

Single Chip Ethernet Controller with General Processor Interface

Preliminary

Version: DM9010-17--DS-P04

Jan. 18, 2006

TXVDD25

Internal regulator 2.5V output for TP TX

5.7 Miscellaneous

16,17,18,

TEST1~TEST4

Operation Mode

Test 1, 2, 3, 4 = (1, 1, 0, 0) in normal application

TEST5

I,PD Internal system clock source

0: use internal 50MHz clock *(Suggestion)

1: use CLK20MO pin

68,69,70,

71,

74,75,77

GP0~6

I/O,PD General I/O Ports

Registers GPCR and GPR can program these pins

The GPIO0 is an output mode, and output data high at default is to power

down internal PHY and other external MII device

GP1~3 defaults are input ports, GP 0,4~6 force to output ports.

LINK_O

O,PD Cable Link Status Output. Active High

This pin is also used as a strap pin to define whether the MII interface is a

reversed MII interface (pulled high) or a normal MII interface (not pulled

high). This pin has a pulled down resistor about 60k ohm internally.

WAKE

O,PD Issue a wake up signal when wake up event happens

This pin has a pulled down resistor about 60k ohm internally.

PW_RST#

Power on Reset

Active low signal to initiate the DM9010

The DM9010 is ready after 5us when this pin deasserted

5.8 Power Pins

5,20,55,

72,90,73

DVDD

Digital VDD

15,23,42,

58,63,81,

99,76

GND

Digital GND

5.9 strap pins table

1: pull-high 1K~10K,

0: floating.

Pin No.

Pin Name

Description

MDC

Polarity of INT

1: INT pin low active;

0: INT pin high active

EEDO

DATA Bus Width

WAKE

EEDO

data width

16-bit

32-bit

8-bit

reserved

EECS

LED Mode

When it is pulled high, the LED mode is mode 1; Otherwise it is mode 0

52,51,

TXD[2:0]

IO base address. (not available in 32-bit mode)

IO base = (strap pin value of TXD [2:0]) * 10H + 300H

LINK_O

Reverse MII

DM9010EP Datasheet(PDF) 14 Page - Davicom Semiconductor, Inc.

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