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DM9010EP Datasheet(PDF) 25 Page - Davicom Semiconductor, Inc.

Part # DM9010EP
Description  10/100 Mbps Single Chip Ethernet Controller with General Processor Interface
PDF  62 Pages
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Manufacturer  DAVICOM [Davicom Semiconductor, Inc.]
Direct Link  http://www.davicom.com.tw
Logo DAVICOM - Davicom Semiconductor, Inc.

DM9010EP Datasheet(HTML) 25 Page - Davicom Semiconductor, Inc.

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DM9010
Single Chip Ethernet Controller with General Processor Interface
Preliminary
25
Version: DM9010-17--DS-P04
Jan. 18, 2006
1~0
ETT
HPS0,RW
Early Transmit Threshold
Start transmit when data write to TX FIFO reach the byte-count threshold
Bit-1 bit-0
threshold
----- ----
-------------
0
0
: 12.5%
0
1
: 25%
1
0
: 50%
1
1
: 75%
6.29 Transmit Check Sum Control Register ( 31H )
Bit
Name
Default
Description
7~3
RESERVED
0,RO
Reserved
2
UDPCSE
HPS0,RW
UDP CheckSum Generation Enable
1
TCPCSE
HPS0,RW
TCP CheckSum Generation Enable
0
IPCSE
HPS0,RW
IP CheckSum Generation Enable
6.30 Receive Check Sum Control Status Register ( 32H )
Bit
Name
Default
Description
7
UDPS
HPS0,RO UDP CheckSum Status
0: checksum OK, if UDP packet
6
TCPS
HPS0,RO TCP CheckSum Status
0: checksum OK, if TCP packet
5
IPS
HPS0,RO IP CheckSum Status
0: checksum OK, if IP packet
4
UDPP
HPS0,RO UDP Packet
3
TCPP
HPS0,RO TCP Packet
2
IPP
HPS0,RO IP Packet
1
RCSEN
HPS0,R
W
Receive CheckSum Checking Enable
When set, the checksum status will store in packet first byte of status header.
0
DCSE
HPS0,R
W
Discard CheckSum Error Packet
When set, if IP/TCP/UDP checksum field is error, this packet will be discarded.
6.31 External PHYceiver Address Register ( 33H )
Bit
Name
Default
Description
7
ADR_EN
HPS0,R
W
External PHY Address Enabled
When set in external MII mode, the external PHYceiver address is defined at bit
4~0.
6~5
Reserved
HPS0,RO Reserved
4~0
EPHYADR
HPS01,R
W
External PHY Address Bit 4~0
The PHY address in external MII mode.
6.32 General Purpose Control Register 2 ( 34H )
Bit
Name
Default
Description



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