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DM9010EP Datasheet(PDF) 33 Page - Davicom Semiconductor, Inc. |
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DM9010EP Datasheet(HTML) 33 Page - Davicom Semiconductor, Inc. |
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33 / 62 page ![]() DM9010 Single Chip Ethernet Controller with General Processor Interface Preliminary 33 Version: DM9010-17--DS-P04 Jan. 18, 2006 affected by the management entity that clears this bit 0 = Normal operation 0.8 Duplex mode 1,RW Duplex Mode 1 = Full duplex operation. Duplex selection is allowed when Auto-negotiation is disabled (bit 12 of this register is cleared). With auto-negotiation enabled, this bit reflects the duplex capability selected by auto-negotiation 0 = Normal operation 0.7 Collision test 0,RW Collision Test 1 = Collision test enabled. When set, this bit will cause the COL signal to be asserted in response to the assertion of TX_EN in internal MII interface. 0 = Normal operation 0.6-0.0 Reserved 0,RO Reserved Read as 0, ignore on write 8.2 Basic Mode Status Register (BMSR) - 01 Bit Bit Name Default Description 1.15 100BASE-T4 0,RO/P 100BASE-T4 Capable 1 = DM9010 is able to perform in 100BASE-T4 mode 0 = DM9010 is not able to perform in 100BASE-T4 mode 1.14 100BASE-TX full-duplex 1,RO/P 100BASE-TX Full Duplex Capable 1 = DM9010 is able to perform 100BASE-TX in full duplex mode 0 = DM9010 is not able to perform 100BASE-TX in full duplex mode 1.13 100BASE-TX half-duplex 1,RO/P 100BASE-TX Half Duplex Capable 1 = DM9010 is able to perform 100BASE-TX in half duplex mode 0 = DM9010 is not able to perform 100BASE-TX in half duplex mode 1.12 10BASE-T full-duplex 1,RO/P 10BASE-T Full Duplex Capable 1 = DM9010 is able to perform 10BASE-T in full duplex mode 0 = DM9010 is not able to perform 10BASE-TX in full duplex mode 1.11 10BASE-T half-duplex 1,RO/P 10BASE-T Half Duplex Capable 1 = DM9010 is able to perform 10BASE-T in half duplex mode 0 = DM9010 is not able to perform 10BASE-T in half duplex mode 1.10-1.7 Reserved 0,RO Reserved Read as 0, ignore on write |
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