DM9010EP datasheet(17/62 Pages) DAVICOM

17 / 62 page

DM9010

Single Chip Ethernet Controller with General Processor Interface

Preliminary

Version: DM9010-17--DS-P04

Jan. 18, 2006

RO = Read only

RW = Read/Write

R/C = Read and Clear

RW/C1=Read/Write and Cleared by write 1

WO = Write only

Reserved bits are shaded and should be written with 0.

Reserved bits are undefined on read access.

6.1 Network Control Register (00H)

Bit

Name

Default

Description

EXT_PHY

PH0,RW

Selects external PHY when set. Selects Internal PHY when clear. This bit will not

be affected after software reset

WAKEEN

P0,RW

Wakeup Event Enable

When set, it enables the wakeup function. Clearing this bit will also clears all

wakeup event status

This bit will not be affected after a software reset

RESERVED

0,RO

Reserved

FCOL

PHS0,RW Force Collision Mode, used for testing

FDX

PHS0,RW Full-Duplex Mode. Read only on Internal PHY mode. R/W on External PHY mode

2:1

LBK

PHS00,

Loopback Mode

Bit

2 1

Normal

MAC Internal Loopback

Internal PHY 100M mode digital Loopback

(Reserved)

RST

PH0,RW

Software reset and auto clear after 10us

6.2 Network Status Register (01H)

Bit

Name

Default

Description

SPEED

X,RO

Media Speed 0:100Mbps 1:10Mbps, when Internal PHY is used. This bit has no

meaning when LINKST=0

LINKST

X,RO

Link Status 0:link failed 1:link OK, when Internal PHY is used

WAKEST

P0,

RW/C1

Wakeup Event Status. Clears by read or write 1

This bit will not be affected after software reset

RESERVED

0,RO

Reserved

TX2END

PHS0,

RW/C1

TX Packet 2 Complete Status. Clears by read or write 1

Transmit completion of packet index 2

TX1END

PHS0,

RW/C1

TX Packet 1 Complete status. Clears by read or write 1

Transmit completion of packet index 1

RXOV

PHS0,RO RX FIFO Overflow

RESERVED

0,RO

Reserved

6.3 TX Control Register (02H)

Bit

Name

Default

Description

RESERVED

0,RO

Reserved

TJDIS

PHS0,RW

Transmit Jabber Disable

When set, the transmit Jabber Timer (2048 bytes) is disabled. Otherwise it is Enable

EXCECM

PHS0,RW Excessive Collision Mode Control : 0:aborts this packet when excessive collision

counts more than 15, 1: still tries to transmit this packet

PAD_DIS2

PHS0,RW PAD Appends Disable for Packet Index 2

CRC_DIS2

PHS0,RW CRC Appends Disable for Packet Index 2

DM9010EP Datasheet(PDF) 17 Page - Davicom Semiconductor, Inc.

DM9010EP Datasheet(HTML) 17 Page - Davicom Semiconductor, Inc.

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