DM9010EP datasheet(27/62 Pages) DAVICOM

27 / 62 page

DM9010

Single Chip Ethernet Controller with General Processor Interface

Preliminary

Version: DM9010-17--DS-P04

Jan. 18, 2006

6.37 INT Pin Control Register ( 39H )

Bit

Name

Default

Description

7:2

Reserved

PS0,RO

Reserved

INT_TYPE

PET0,RW

INT Pin Output Type Control

1: INT Open-Collector output

0: INT direct output

INT_POL

PET0,RW

INT Pin Polarity Control

1: INT active low

0: INT active high

6.38 Monitor Register 1 ( 40H )

Bit

Name

Default

Description

BWIDTH

T0,RO

8-bit Data Strap Latch Status

DWIDTH

T0,RO

32-bit Data Strap Latch Status

INTOC

ET0,RO

INT Open-Collect Pin Status

INTP

ET0,RO

INT Polarity Pin Status

IO16OC

E0,RO

IO16/32 Open-Collect Pin Status

IO16P

E0,RO

IO16/32 Polarity Pin Status

ILEDM

ET0,RO

LED Mode Status

MDIX

ET0,RO

MDIX Strap Pin Status

6.39 Monitor Register 2 ( 41H )

Bit

Name

Default

Description

7~4

RESERVED

0,RO

Reserved

NOEEP

T0,RO

NO Load EEPROM Strap Pin Status

EXTMII

T0,RO

External MII Strap Pin Status

PHYUP

T0,RO

PHY Power-Up Strap Pin Status

RMII

T0,RO

Reverse MII strap Pin Status

6.40 System Clock Turn ON Control Register ( 50H )

Bit

Name

Default

Description

7:1

Reserved

DIS_CLK

P0,W

Stop Internal System Clock

1: internal system clock turn off, internal PHYceiver also power down

0: internal system clock is ON

6.41 Resume System Clock Control Register ( 51H )

When the INDEX port set to 51H, the internal system clock is turn ON.

6.42 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H)

Bit

Name

Default

Description

7:0

MRCMDX

X,RO

Read data from RX SRAM. After the read of this command, the read pointer of

internal SRAM is unchanged. And the DM9010 starts to pre-fetch the SRAM data

to internal data buffers.

DM9010EP Datasheet(PDF) 27 Page - Davicom Semiconductor, Inc.

DM9010EP Datasheet(HTML) 27 Page - Davicom Semiconductor, Inc.

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