BQ24155 datasheet(4/30 Pages) TI

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bq24155

SLUS942 – FEBRUARY 2010

www.ti.com

ELECTRICAL CHARACTERISTICS

Circuit of Figure 1, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (charger mode operation), TJ = 0°C to 125°C, TJ = 25°C for

typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT CURRENTS

VBUS > VBUS(min), PWM switching

VBUS > VBUS(min), PWM NOT switching

0°C < TJ < 85°C, VBUS = 5 V, HZ_MODE = 1,

V(AUXPWR) > V(LOWV), SCL, SDA, ISEL = 0 V or

I(VBUS)

VBUS supply current control

1.8 V

0°C < TJ < 85°C, VBUS = 5 V, HZ_MODE = 1,

V(AUXPWR) < V(LOWV), 32 S mode, SCL, SDA, ISEL

= 0 V or 1.8 V

Leakage current from battery to

0°C < TJ < 85°C, V(AUXPWR) = 4.2 V, High

Ilkg

VBUS pin

impedance mode

0°C < TJ < 85°C, V(AUXPWR) = 4.2 V, High

Battery discharge current in High

impedance mode,

Impedance mode, (CSIN,

VBUS = 0 V,

CSOUT, AUXPWR, SW pins)

SCL, SDA, ISEL = 0 V or 1.8 V

VOLTAGE REGULATION

V(OREG)

Output charge voltage

Operating in voltage regulation, programmable

3.5

4.44

TA = 25°C

–0.5%

0.5%

Voltage regulation accuracy

–1%

CURRENT REGULATION (FAST CHARGE)

Output charge current

V(LOWV) ≤ V(AUXPWR) < V(OREG), VBUS > V(SLP),

550

IO(CHARGE)

1250

programmable range

R(SNS) = 68 mΩ Programmable

Regulation accuracy for charge

20 mV

≤ V(IREG) ≤ 40 mV

–5%

current across R(SNS)

40 mV < V(IREG)

–3%

V(IREG) = IO(CHARGE) × R(SNS)

WEAK BATTERY DETECTION

V(LOWV)

Weak battery voltage threshold

Programmable

3.4

3.7

programmable range

Weak battery voltage accuracy

–5%

Hysteresis for V(LOWV)

Battery voltage falling

100

Deglitch time for weak battery

Rising voltage, 2 mV overdrive, tRISE = 100 ns

threshold

ISEL PIN LOGIC LEVEL

VIL

Input low threshold level

0.4

VIH

Input high threshold level

1.3

CHARGE TERMINATION DETECTION

Termination charge current

V(AUXPWR) > V(OREG) – V(RCH),

I(TERM)

400

programmable range

VBUS > V(SLP), R(SNS) = 68 mΩ Programmable

Deglitch time for charge

Both rising and falling, 2 mV overdrive, tRISE, tFALL

termination

= 100 ns

3.4 mV

≤ V(IREG_TERM) < 6.8 mV

–25%

25%

Voltage regulation accuracy for

termination current across R(SNS)

6.8 mV

≤ V(IREG_TERM) < 13.6 mV

–10%

10%

V(IREG_TERM) = IO(TERM) × R(SNS)

13.6 mV

≤ V(IREG_TERM) ≤ 27.2 mV

–5%

INPUT POWER SOURCE DETECTION

Input voltage lower limit

Input power source detection, Input voltage falling

3.6

3.8

Deglitch time for VBUS rising

VIN(min)

Rising voltage, 2 mV overdrive, tRISE = 100 ns

above VIN(min)

Hysteresis for VIN(min)

Input voltage rising

100

200

tINT

Detection Interval

Input power source detection

INPUT CURRENT LIMITING

IIN = 100 mA

IIN

Input current limiting threshold

USB charge mode

IIN = 500 mA

450

475

500

VREF BIAS REGULATOR

VBUS >VIN(min) or V(AUXPWR) > V(BAT)min,

VREF

Internal bias regulator voltage

6.5

I(VREF) = 1 mA, C(VREF) = 1 mF

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