STARTCondition

DATA

CLK

STOP Condition

S

P

bq24155

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SLUS942 – FEBRUARY 2010

To reduce the output voltage ripple, a ceramic capacitor with the capacitance between 4.7 mF and 47 mF is

Pre-Regulator Application

Figure 2 shows a typical pre-regulator application that the bq24155 operates as a DC/DC converter, with the

termination disabled. In this application, the host charge controller controls switch Q to achieve pulse-charging

compensation design ensures the stable operation when the host-controlled switch Q is turned off. With the input

overvoltage protection, output current regulation and high efficiency power conversion, the bq24155 is an ideal

choice for pre-regulator used in pulse charging applications.

SERIAL INTERFACE DESCRIPTION

January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the

through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal

processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The

master also generates specific conditions that indicate the START and STOP of data transfer. A slave device

receives and/or transmits data on the bus under control of the master device.

The bq24155 device works as a slave and is compatible with the following data transfer modes, as defined in the

in write mode). The interface adds flexibility to the battery charge solution, enabling most functions to be

programmed to new values depending on the instantaneous application requirements. Register contents remain

of SCL. The device has no noise or glitch filtering on SCL, so SCL input needs to be clean. Therefore, it is

recommended that SDA changes while SCL is LOW.

The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the

F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to

as the HS-mode. The bq24155 device only supports 7-bit addressing. The device 7-bit address is defined as

‘1101011’ (6BH).

F/S Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

recognize a start condition.

Figure 15. START and STOP Condition

The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W

on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires

the SDA line to be stable during the entire high period of the clock pulse (see Figure 16). All devices recognize

the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a

matching address generates an acknowledge (see Figure 16) by pulling the SDA line low during the entire high

period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a

slave has been established.

Copyright © 2010, Texas Instruments Incorporated

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