LPC1111 datasheet(23/59 Pages) NXP

23 / 59 page

LPC1111_12_13_14_1

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Product data sheet

Rev. 01 — 16 April 2010

23 of 59

NXP Semiconductors

LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

• Counter or timer operation.

• One capture channel per timer, that can take a snapshot of the timer value when an

input signal transitions. A capture event may also generate an interrupt.

• Four match registers per timer that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

7.13 System tick timer

The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).

7.14 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a selectable time

period.

7.14.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 32-bit timer with internal prescaler.

• Selectable time period from (Tcy(WDCLK) × 256 × 4) to (Tcy(WDCLK) × 232 × 4) in

multiples of Tcy(WDCLK) × 4.

• The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator

(IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential

timing choices of Watchdog operation under different power reduction conditions. It

also provides the ability to run the WDT from an entirely internal source that is not

dependent on an external crystal and its associated components and wiring for

increased reliability.

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