SC68C752B datasheet(29/48 Pages) NXP

29 / 48 page

SC68C752B_4

Product data sheet

Rev. 04 — 20 January 2010

29 of 48

NXP Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

7.10 Enhanced Feature Register (EFR)

This 8-bit register enables or disables the enhanced features of the UART. Table 20

shows the Enhanced Feature Register bit settings.

7.11 Divisor latches (DLL, DLM)

These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock

in the baud rate generator. DLM stores the most significant part of the divisor. DLL stores

the least significant part of the divisor.

Note that DLL and DLM can only be written to before Sleep mode is enabled, that is,

before IER[4] is set.

7.12 Transmission Control Register (TCR)

This 8-bit register is used to store the receive FIFO threshold levels to stop/start

transmission during hardware/software flow control. Table 21 shows transmission control

TCR trigger levels are available from 0 bytes to 60 bytes with a granularity of four.

Table 20.

Enhanced Feature Register bits description

Bit

Symbol

Description

EFR[7]

CTS flow control enable.

logic 0 = CTS flow control is disabled (normal default condition)

logic 1 = CTS flow control is enabled. Transmission will stop when a HIGH

signal is detected on the CTSn pin.

6EFR[6]

RTS flow control enable.

logic 0 = RTS flow control is disabled (normal default condition)

logic 1 = RTS flow control is enabled. The RTSn pin goes HIGH when the

receiver FIFO halt trigger level TCR[3:0] is reached, and goes LOW when the

receiver FIFO resume transmission trigger level TCR[7:4] is reached.

EFR[5]

Special character detect.

logic 0 = special character detect disabled (normal default condition)

logic 1 = special character detect enabled. Received data is compared with

Xoff2 data. If a match occurs, the received data is transferred to FIFO and

IIR[4] is set to a logic 1 to indicate a special character has been detected.

EFR[4]

Enhanced functions enable bit.

logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4],

MCR[7:5]

logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5]

can be modified, that is, this bit is therefore a write enable

3:0

EFR[3:0]

Combinations of software flow control can be selected by programming these

bits. See Table 4 “Software flow control options (EFR[3:0])” on page 9.

Table 21.

Transmission Control Register bits description

Bit

Symbol

Description

7:4

TCR[7:4]

receive FIFO trigger level to resume transmission (0 bytes to 60 bytes).

3:0

TCR[3:0]

receive FIFO trigger level to halt transmission (0 bytes to 60 bytes).

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