SC68C752B datasheet(16/48 Pages) NXP

16 / 48 page

SC68C752B_4

Product data sheet

Rev. 04 — 20 January 2010

16 of 48

NXP Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6.6.2 Block DMA transfers (DMA mode 1)

Figure 11 shows TXRDYn and RXRDYn in DMA mode 1.

6.6.2.1

Transmitter

TXRDYn is active when there is a trigger level number of spaces available. It becomes

inactive when the FIFO is full.

6.6.2.2

Receiver

RXRDYn becomes active when the trigger level has been reached, or when a time-out

interrupt occurs. It will go inactive when the FIFO is empty or an error in the receive FIFO

is flagged by LSR[7].

6.7 Sleep mode

Sleep mode is an enhanced feature of the SC68C752B UART. It is enabled when EFR[4],

the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when:

• The serial data input line, RXn, is idle (see Section 6.8 “Break and time-out

conditions”).

• The transmit FIFO and transmit shift register are empty.

• There are no interrupts pending except THR and time-out interrupts.

Remark: Sleep mode will not be entered if there is data in the receive FIFO.

In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are

clocked using these clocks, the power consumption is greatly reduced. The UART will

wake up when any change is detected on the RXn line, when there is any change in the

state of the modem input pins, or if data is written to the transmit FIFO.

Remark: Writing to the divisor latches, DLL and DLM, to set the baud clock, must not be

done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4]

before writing to DLL or DLM.

Fig 11. TXRDYn and RXRDYn in DMA mode 1

transmit

wrptr

TXRDYn

FIFO full

TXRDYn

receive

rdptr

FIFO EMPTY

RXRDYn

002aaa234

trigger

level

trigger

level

at least one

location filled

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