SC68C752B datasheet(5/48 Pages) NXP

5 / 48 page

SC68C752B_4

Product data sheet

Rev. 04 — 20 January 2010

5 of 48

NXP Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

5.2 Pin description

Table 2.

Pin description

Symbol

Type

Description

LQFP48 HVQFN32

Address 0 select bit. Internal registers address selection.

Address 1 select bit. Internal registers address selection.

Address 2 select bit. Internal registers address selection.

Address 3. A3 is used to select Channel A or Channel B. A logic LOW selects

Channel A, and a logic HIGH selects Channel B. (See Table 3.)

CDA

Carrier Detect (active LOW). These inputs are associated with individual UART

Channel A and Channel B. A logic LOW on these pins indicates that a carrier has

been detected by the modem for that channel. The state of these inputs is

reflected in the Modem Status Register (MSR).

CDB

Chip Select (active LOW). This pin enables data transfers between the user

CPU and the SC68C752B for the channel(s) addressed. Individual UART

sections (A, B) are addressed by A3. See Table 3.

CTSA

Clear to Send (active LOW). These inputs are associated with individual UART

Channel A and Channel B. A logic 0 (LOW) on the CTSn pins indicates the

modem or data set is ready to accept transmit data from the SC68C752B. Status

can be tested by reading MSR[4]. These pins only affect the transmit and receive

operations when auto-CTS function is enabled via the Enhanced Feature

CTSB

I/O

Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for

transferring information to or from the controlling CPU. D0 is the least significant

bit and the first data bit in a transmit or receive serial data stream.

I/O

DSRA

Data Set Ready (active LOW). These inputs are associated with individual

UART Channel A and Channel B. A logic 0 (LOW) on these pins indicates the

modem or data set is powered-on and is ready for data exchange with the UART.

The state of these inputs is reflected in the Modem Status Register (MSR).

DSRB

DTRA

Data Terminal Ready (active LOW). These outputs are associated with

individual UART Channel A and Channel B. A logic 0 (LOW) on these pins

indicates that the SC68C752B is powered-on and ready. These pins can be

controlled via the Modem Control Register. Writing a logic 1 to MCR[0] will set the

DTRn output pin to logic 0 (LOW), enabling the modem. The output of these pins

will be a logic 1 after writing a logic 0 to MCR[0], or after a reset.

DTRB

GND

17, 24

13[1]

Signal and power ground.

IRQ

Interrupt Request. Interrupts from UART Channel A and Channel B are

wire-ORed internally to function as a single IRQ interrupt. This pin transitions to a

logic 0 (if enabled by the Interrupt Enable Register) whenever a UART channel(s)

requires service. Individual channel interrupt status can be determined by

addressing each channel through its associated internal register, using CS and

A3. An external pull-up resistor must be connected between this pin and VCC.

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