SC68C752B datasheet(6/48 Pages) NXP

6 / 48 page

SC68C752B_4

Product data sheet

Rev. 04 — 20 January 2010

6 of 48

NXP Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

R/W

A logic LOW on this pin will transfer the contents of the data bus (D[7:0]) from an

external CPU to an internal register that is defined by address bits A[2:0]. A logic

HIGH on this pin will load the contents of an internal register defined by address

bits A[2:0] on the SC68C752B data bus (D[7:0]) for access by an external CPU.

n.c.

12, 25,

29, 37

14, 20

not connected

OPA

User defined outputs. This function is associated with individual Channel A and

Channel B. The state of these pins is defined by the user through the software

settings of MCR[3]. OPA/OPB is a logic 0 when MCR[3] is set to a logic 1.

OPA/OPB is a logic 1 when MCR[3] is set to a logic 0. The output of these two

pins is HIGH after reset.

OPB

RESET

Reset (active LOW). This pin will reset the internal registers and all the outputs.

The UART transmitter output and the receiver input will be disabled during reset

time. RESET is an active LOW input.

RIA

Ring Indicator (active LOW). These inputs are associated with individual UART

Channel A and Channel B. A logic 0 on these pins indicates the modem has

received a ringing signal from the telephone line. A LOW-to-HIGH transition on

these input pins generates a modem status interrupt, if enabled. The state of

these inputs is reflected in the Modem Status Register (MSR).

RIB

RTSA

Request to Send (active LOW). These outputs are associated with individual

UART Channel A and Channel B. A logic 0 on the RTSn pin indicates the

transmitter has data ready and waiting to send. Writing a logic 1 in the Modem

Control Register MCR[1] will set this pin to a logic 0, indicating data is available.

After a reset these pins are set to a logic 1. These pins only affect the transmit

and receive operations when auto-RTS function is enabled via the Enhanced

Feature Register (EFR[6]) for hardware flow control operation.

RTSB

RXA

Receive data input. These inputs are associated with individual serial channel

data to the SC68C752B. During the local Loopback mode, these RXn input pins

are disabled and transmit data is connected to the UART receive input internally.

RXB

RXRDYA

Receive Ready (active LOW). RXRDYA or RXRDYB goes LOW when the

trigger level has been reached or the FIFO has at least one character. It goes

HIGH when the receive FIFO is empty.

RXRDYB

TXA

Transmit data A, B. These outputs are associated with individual serial transmit

channel data from the SC68C752B. During the local Loopback mode, the TXn

output pin is disabled and transmit data is internally connected to the UART

receive input.

TXB

TXRDYA

Transmit Ready (active LOW). TXRDYA or TXRDYB go LOW when there are at

least a trigger level number of spaces available or when the FIFO is empty. It

goes HIGH when the FIFO is full or not empty.

TXRDYB

VCC

19, 42

Power supply input.

XTAL1

Crystal or external clock input. Functions as a crystal input or as an external

clock input. A crystal can be connected between XTAL1 and XTAL2 to form an

internal oscillator circuit (see Figure 13). Alternatively, an external clock can be

connected to this pin to provide custom data rates.

XTAL2

Output of the crystal oscillator or buffered clock. (See also XTAL1.) XTAL2 is

used as a crystal oscillator output or a buffered clock output.

Table 2.

Pin description …continued

Symbol

Type

Description

LQFP48 HVQFN32

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