FS6370

9.0 Programming Information

Table 3: Register Map (Note: All register bits are cleared to zero on power-up)

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Byte 15

MUX_D2[1:0]

(selected via SEL_CD = 1)

MUX_C2[1:0]

(selected via SEL_CD = 1)

PDPOST_D

PDPOST_C

PDPOST_B

PDPOST_A

Byte 14

POST_D2[3:0]

(selected via SEL_CD = 1)

POST_C2[3:0]

(selected via SEL_CD = 1)

Byte 13

POST_D1[3:0]

(selected via SEL_CD = 0)

POST_C1[3:0]

(selected via SEL_CD = 0)

Byte 12

POST_B[3:0]

POST_A[3:0]

Byte 11

MUX_D1[1:0]

(selected via SEL_CD = 0)

Reserved (0)

LFTC_C2

(SEL_CD=1)

CP_C2

(SEL_CD=1)

FBKDIV_C2[10:8] M-Counter

(selected via SEL_CD pin = 1)

Byte 10

FBKDIV_C2[7:3] M-Counter

(selected via SEL_CD pin = 1)

FBKDIV_C2[2:0] A-Counter

Byte 9

REFDIV_C2[7:0]

(selected via SEL_CD pin = 1)

Byte 8

MUX_C1[1:0]

(selected via SEL_CD = 0)

PDPLL_C

LFTC_C1

(SEL_CD=0)

CP_C1

(SEL_CD=0)

FBKDIV_C1[10:8] M-Counter

(selected via SEL_CD = 0)

Byte 7

FBKDIV_C1[7:3] M-Counter

(selected via SEL_CD = 0

FBKDIV_C1[2:0] A-Counter

(selected via SEL_CD = 1)

Byte 6

REFDIV_C1[7:0]

(selected via SEL_CD = 0)

Byte 5

MUX_B[1:0]

PDPLL_B

LFTC_B

CP_B

FBKDIV_B[10:8] M-Counter

Byte 4

FBKDIV_B[7:3] M-Counter

FBKDIV_B[2:0] A-Counter

Byte 3

REFDIV_B[7:0]

Byte 2

MUX_A[1:0]

PDPLL_A

LFTC_A

CP_A

FBKDIV_A[10:8] M-Counter

Byte 1

FBKDIV_A[7:3] M-Counter

FBKDIV_A[2:0] A-Counter

Byte 0

REFDIV_A[7:0]

9.1 Control Bit Assignments

If any PLL control bit is altered during device operation, including those bits controlling the reference and feedback dividers, the output

frequency will slew smoothly (in a glitch-free manner) to the new frequency. The slew rate is related to the programmed loop filter time

constant.

However, any programming changes to any mux or post divider control bits will cause a glitch on an operating clock output.

9.1.1. Power-Down

All power-down functions are controlled by enable bits. That is, the bits select which portions of the FS6370 to power-down when the

PD input is asserted. If the power-down bit contains a one, the related circuit will shut down if the PD pin is high (run mode only). When

the PD pin is low, power is enabled to all circuits.

If the power-down bit contains a zero, the related circuit will continue to function regardless of the PD pin state.

Rev. 3 | Page 12 of 28 | www.onsemi.com