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AD5757/AD5737

Preliminary Technical Data

Rev. PrD | Page 14 of 31

THEORY OF OPERATION

The AD5757/AD5737 is a quad, precision digital to current

loop converter designed to meet the requirements of industrial

process control applications. It provides a high precision, fully

integrated, low cost single-chip solution for generating current

loop outputs. The current ranges available are; 0 to 20mA, 0 to

24mA and 4 to 20mA. The desired output configuration is user

selectable via the DAC Control Register.

On chip dynamic power control minimizes package power

dissipation in current mode.

DAC ARCHITECTURE

The DAC core architecture of the AD5757/AD5737 consists of

two matched DAC sections. A simplified circuit diagram is

shown in Figure 13. The 4 MSBs of the 16/12-bit data word are

decoded to drive 15 switches, E1 to E15. Each of these switches

connects 1 of 15 matched resistors to either ground or the

reference buffer output. The remaining 12/8 bits of the data-

word drive switches S0 to S11 /S7 of a 12/8-bit voltage mode R-

2R ladder network.

Figure 13. DAC Ladder Structure

The voltage output from the DAC core is converted to a current

(see Figure 14) which is then mirrored to the supply rail so that

the application simply sees a current source output with respect

to ground.

Figure 14. Voltage to Current conversion circuitry

Reference Buffers

The AD5757/AD5737 can operate with either an external or

internal reference. The reference input has an input range of 4 V

to 5 V, 5 V for specified performance. This input voltage is then

buffered before it is applied to the DAC.

POWER ON STATE OF AD5757/AD5737

On initial power-up of the

AD5757/AD5737 with the Iout pin in

tri-state mode.

SERIAL INTERFACE

The AD5757/AD5737 is controlled over a versatile 3-wire serial

interface that operates at clock rates of up to 30 MHz and is

compatible with SPI®, QSPI™, MICROWIRE™, and DSP

standards. Data coding is always straight binary.

Input Shift Register

The input shift register is 24 bits wide. Data is loaded into the

device MSB first as a 24-bit word under the control of a serial

clock input, SCLK. Data is clocked in on the falling edge of

SCLK.

There are two ways in which the DAC outputs can be updated

as outlined below.

Individual DAC Updating

In this mode, LDAC is held low while data is being clocked into

the DAC Data Register. The addressed DAC output is updated

on the rising edge of SYNC.

Simultaneous Updating of All DACs

In this mode, LDAC is held high while data is being clocked

into the DAC Data Register. Only the first write to each

channels data register will be valid after LDAC is brought high.

Any subsequent writes while LDAC is still held high will be

ignored. All the DAC outputs are updated by taking LDAC low

any time after SYNC has been taken high.

Figure 15. Simplified Serial Interface of Input Loading Circuitryfor One DAC

Channel

8-12 BIT R-2R LADDER

FOUR MSBs DECODED INTO

15 EQUAL SEGMENTS

S7/S11

E15

VOUT

12-/16-BIT

DAC

VBOOST

IOUT

RSET

VOUT

DAC

INTERFACE

LOGIC

OUTPUT

I/V AMPLIFIER

LDAC

SDO

SDIN

16-BIT

DAC

VREFIN

SYNC

INPUT

SCLK

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