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Preliminary Technical Data

AD5757/AD5737

Rev. PrD | Page 25 of 31

FEATURES

OUTPUT FAULT

The AD5757/AD5737 is equipped with a FAULT pin, this is an

active low open-drain output allowing several AD5757/AD5737

devices to be connected together to one pull-up resistor for

global fault detection. The FAULT pin is forced active by any

one of the following fault scenarios;

1) The Voltage at IOUT attempts to rise above the

compliance range, due to an open-loop circuit or

insufficient power supply voltage. The internal

circuitry that develops the fault output avoids using a

comparator with “window limits” since this would

require an actual output error before the FAULT

output becomes active. Instead, the signal is generated

when the internal amplifier in the output stage has less

than approximately one volt of remaining drive

capability. Thus the FAULT output activates slightly

before the compliance limit is reached. Since the

comparison is made within the feedback loop of the

output amplifier, the output accuracy is maintained by

its open-loop gain and an output error does not occur

before the FAULT output becomes active.

2) An interface error is detected due to a PEC failure. See

Packet Error Checking section.

3) If the core temperature of the AD5757/AD5737

exceeds approx. 150°C.

The OPEN CCT and OVER TEMP bits of the Status Register

are used in conjunction with the FAULT output to inform the

user which one of the fault conditions caused the FAULT output

to be activated.

DIGITAL OFFSET AND GAIN CONTROL

Each DAC channel has a gain (M) and offset (C) register, which

allow trimming out of the gain and offset errors of the entire

signal chain. Data from the DAC Data Register is operated on

by a digital multiplier and adder controlled by the contents of

the M and C registers. The calibrated DAC data is then stored

in the DAC2 register.

Figure 18. Digital Offset and Gain control

Although this diagram indicates a multiplier and adder for each

channel, there is only one multiplier and one adder in the device,

and they are shared among all 4 channels. This has implications

for the update speed when several channels are updated at once.

Each time data is written to the M or C register the output is not

automatically updated. Rather, the next write to the DAC

channel will use these M&C values to perform a new calibration

and automatically update the channel.

Data output from the DAC2 register is routed to the final DAC

calibrate the gain/offset is firstly to calibrate out the gain and

then calibrate the offset.

The value (in decimal) that is written to the DAC register can

be calculated by:

)

(

−

Code

gister

DAC

where:

D is the code loaded to the DAC channels input register.

M is the code in Gain Register − default code = 216 – 1

C is the code in Offset Register − default code = 215

STATUS READBACK DURING WRITE

The AD5757/AD5737 has the ability to read back the Status

enabled via the STATREAD bit in the Main Control Register.

This allows the user to continuously monitor the Status Register

and act quickly in the case of a fault.

When Status Readback During Write is enabled the contents of

the 16bit Status register (See Table 36) is outputted on the SDO

pin as indicated in Figure 4.

The AD5757/AD5737 will power up with this feature disabled.

When this is enabled the normal readback feature is not

available, except of the status register. To readback any other

sequence. STATREAD may be set high again after the register

read.

ASYNCHRONOUS CLEAR

CLEAR is an active high edge sensitive input that allows the

output to be cleared to a pre programmed 16 bit code. This code

is user programmable via a per-channel 16 bit Clear Code

In order for a channel to clear, that channel must be enabled to

be cleared via the CLR_EN bit in the channels DAC Control

output will remain in its current state independent of the

CLEAR pin level.

DAC

INPUT

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