Preliminary Technical Data

AD5757/AD5737

Rev. PrD | Page 19 of 31

Table 18. AD5757 Offset Register options

Offset Adjustment

OF15

OF14

OF13

OF12 to OF4

OF3

OF2

OF1

OF0

+32768 LSBs

1

1

1

1

1

1

1

1

+32767 LSBs

1

1

1

1

1

1

0

0

-

-

-

-

-

-

-

-

No Adjustment (default)

1

0

0

0

0

0

0

0

-

-

-

-

-

-

-

-

−32767 LSBs

0

0

0

0

0

0

0

0

−32768 LSBs

0

0

0

0

0

0

0

0

Table 19. AD5737 Offset Register options

Offset Adjustment

OF15

OF14

OF13

OF12 to OF4

OF3

OF2

OF1

OF0

+8192 LSBs

1

1

1

1

X

X

X

X

+8191 LSBs

1

1

1

1

X

X

X

X

-

-

-

-

X

X

X

X

No Adjustment (default)

1

0

0

0

X

X

X

X

-

-

-

-

X

X

X

X

−8191 LSBs

0

0

0

1

X

X

X

X

−8192 LSBs

0

0

0

0

X

X

X

X

CLEAR CODE REGISTER

There is a per channel Clear Code Register. The Clear Code Register is 16 bits wide and is addressed by setting the DREG bits to’1,1,0’. It

is also possible, via software, to enable/disable on a per channel basis which channels will be cleared when the CLEAR pin is activated.

The default clear code is all 0’s. See Features section for more information.

Table 20. Programming AD5757 Clear Code Register

D23

D22

D21

D20

D19

D18

D17

D16

D15 to D0

R/W DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 CLEAR CODE

0

DEVICE ADDRESS

110

DAC Channel Address

DATA

Table 21. Programming the AD5737 Offset Register

R/W DUT_

AD1

DUT_

AD0

DREG2

DREG1

DREG0

DAC_

AD1

DAC_

AD0

D15 to D4

D3

D2 D1

D0

0

DEVICE ADDRESS 110

DAC Channel Address CLEAR CODE

0

0

0

0