IR3523MPBF datasheet(3/37 Pages) IRF

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IR3523

Page 3 of 37

June 20, 2008

PIN#

PIN SYMBOL

PIN DESCRIPTION

FB2

Output 2 Error Amplifier inverting input

VOUT2

Output 2 remote sense amplifier output.

VOSEN2+

Output 2 remote sense amplifier input. Connect to output at the load.

VOSEN2-

Output 2 remote sense amplifier input. Connect to ground at the load.

VOSEN1-

Output 1 remote sense amplifier input. Connect to ground at the load.

VOSEN1+

Output 1 remote sense amplifier input. Connect to output at the load.

VOUT1

Output 1 remote sense amplifier output.

FB1

Inverting input to the output 1 Error Amplifier

EAOUT1

Output 1 error amplifier output

OCSET1

Programs the output 1 constant converter output current limit and hiccup over-

current threshold through an external resistor tied to VDAC1 and an internal

current source from this pin. Over-current protection can be disabled by

connecting a resistor from this pin to VDAC1 to program the threshold higher

than the possible signal into the IIN pin from the phase ICs but no greater than

5V (do not float this pin as improper operation will occur).

VDAC1

Output 1 reference voltage programmed by the VID inputs and error amplifier

non-inverting input. Connect an external RC network to LGND to program

dynamic VID slew rate and provide compensation for the internal buffer

amplifier.

SS/DEL1

Programs output 1 startup and over current protection delay timing. Connect an

external capacitor to LGND to program.

IIN1

Output 1 average current input from the output 1 phase IC(s). This pin is also

used to communicate over voltage condition to phase ICs.

VDRP1

Output 1 Buffered IIN signal. Connect an external RC network to FB1 to

program converter output impedance.

ROSC/OVP

Connect a resistor to LGND to program oscillator frequency and OCSET,

VDAC1 and VREF2 bias currents. Oscillator frequency equals switching

frequency per phase. The pin voltage is 0.6V during normal operation and

higher than 1.6V if over-voltage condition is detected.

PG1

Open collector output. Asserted when Output 1 is regulated.

LGND

Local Ground for internal circuitry and IC substrate connection.

CLKOUT

Clock output at switching frequency multiplied by phase number. Connect to

CLKIN pins of phase ICs.

PHSOUT

Phase clock output at switching frequency per phase. Connect to PHSIN pin of

the first phase IC.

PHSIN

Feedback input of phase clock. Connect to PHSOUT pin of the last phase IC.

VCCL

Output of the voltage regulator, and power input for clock oscillator circuitry.

Connect a decoupling capacitor to LGND.

VCCLFB

Non-inverting input of the voltage regulator error amplifier. Output voltage of the

regulator is programmed by the resistor divider connected to VCCL.

VCCLDRV

Output of the VCCL regulator error amplifier to control external transistor. The

pin senses the converter input voltage through a resistor.

PG2

Open collector output. Asserted when Output 2 output is regulated.

38, 39,

VID2_0,

VID2_1, VID2_2

VID inputs for Output 2

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