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IR3523MPBF Datasheet(PDF) 9 Page - International Rectifier |
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IR3523MPBF Datasheet(HTML) 9 Page - International Rectifier |
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9 / 37 page  IR3523 Page 9 of 37 June 20, 2008 IR3523 block diagram 175k VDAC2 UV2 SS/DEL1 175k 3.0V VID1 SAMPLE AND DELAY COMPARATOR OV1 OV UV2 SSCLF2 SSCLF1 + - DLY OUT1 VCCLDRV SET DOMINANT 50mV + - OV1 250nS BLANKING DYNAMIC DOWN VID2 INTERNAL VDAC 1.0V VID2_2 VID2_1 OV1_2 VID2 VID3 VID2_0 VID0 VID1 VID2 VID3 UV1 VID INPUT COMPARATORS (1 of 3 SHOWN) S R Q INTERNAL VDAC DIGITAL TO ANALOG CONVERTERS DYNAMIC DOWN VID1 1.0V VID1_3 VID1_4 VID1_2 VID3 VID0 VID2 VID3 VID1 VID2 S R Q ENABLE2 PG2 OV2 VBOOT SSCLF2 PG2 OV1_2 275mV 315mV VOUT2 UV COMPARATOR 275mV 315mV VOUT1 UV COMPARATOR SET DOMINANT UV CLEARED FAULT LATCH1 25k S R Q OPEN DAISY DIS IDCHG 4.5uA + - VDAC2 VOSEN2- VOSEN2+ IIN2 OCSET2 FB2 EAOUT2 SS/DEL1 47uA VCCL IDCHG1 VCCL + - 3.9V SS/DEL CLEARED FAULT LATCH1 RESET DOMINANT POWER-UP OK LATCH DELAY COMPARATOR SET DOMINANT DISCHARGE COMPARATOR 80mV 120mV IVOSEN- VIDSEL 0.2V OC1 AFTER VRRDY IROSC DISABLE2 OPEN SENSE1 ICHG 50uA OVER VOLTAGE COMPARATOR VDAC BUFFER AMPLIFIER ERROR AMPLIFIER FLT1 400k (1.1V) VDAC1 DLY OUT1 ISINK ISOURCE REMOTE SENSE AMPLIFIER IVOSEN2- IVOSEN2+ 200mV 0.4V VCCL*0.9 1.4V SOFT START CLAMP DETECTION PULSE1 125mV OC LIMIT COMPARATOR 4 OPEN SENSE LINE DETECT COMPARATORS 60mV VCCL RESET IOCSET OPEN SENSE LINE2 0.3V VDAC1 + - IROSC S R Q 47uA + - IDCHG2 S R Q Q OPEN CONTROL2 PG1 400k 25k OV + - DIS VCCL + - DIS 25k UV CLEARED FAULT LATCH2 SET DOMINANT + - VCCL 25k S R Q DIS PHSOUT DYNAMIC VID1 DOWN DETECT COMPARATOR 8 Pulse Delay IROSC OPEN CONTROL LOOP COMPARATOR OPEN DAISY PHSOUT DLY OUT1 DIS IDCHG 4.5uA OC2 Bf VRRDY VCCL UVLO OV2 PHSOUT CLKOUT LGND ROSC PHSIN CLKOUT FAULT PHSIN IROSC PHSOUT VID0 ROSC BUFFER AMPLIFIER CURRENT SOURCE GENERATOR OC1 Bf VRRDY OPEN DAISY CHAIN 0.6V OC DELAY COUTER IROSC DIS reset reset PHSOUT DIS DIS DIS OC DELAY COUTER IROSC DIS DIS PHSOUT OV2 DLY OUT2 FAULT LATCH 1 DLY OUT2 S R Q Q 0.86 DCHG1 DIS VOUT2 VCCL UVLO FLT2 DETECTION PULSE1 OV1 + - 25k SS/DEL2 + - + - PG1 VDRP1 VCCLDRV VCCLFB VCCL ENABLE1 VOSEN1- VOSEN1+ VOUT1 OCSET1 FB1 EAOUT1 VDAC1 IIN1 VCCL VCCL DISABLE1 IVOSEN- VIDSEL IROSC IROSC ERROR AMPLIFIER DELAY COMPARATOR SET DOMINANT TBS SS/DEL CLEARED FAULT LATCH2 FLT1 SAMPLE DELAY 1.65V 1.0V ENABLE COMPARATOR VDAC BUFFER AMPLIFIER VCCL REGULATOR AMPLIFIER OVER VOLTAGE COMPARATOR 250nS BLANKING VCCL UVL COMPARATOR REMOTE SENSE AMPLIFIER VDRP AMPLIFIER 0.94 1.2V POWER-UP OK LATCH ISINK ISOURCE DIS 50mV 0.2V DISCHARGE COMPARATOR 80mV 120mV RESET DOMINANT VIDSEL VCCL*0.9 IVOSEN1- IVOSEN1+ 200mV 1.2V 0.4V SOFT START CLAMP IFB OC LIMIT COMPARATOR 1.4V 4 OPEN SENSE LINE DETECT COMPARATORS 60mV 125mV FLT2 50uA OPEN SENSE LINE1 OC2 AFTER VRRDY DIS DETECTION PULSE2 VDAC2 IOCSET ICHG 0.3V 8 Pulse Delay VCCL RESET INTERNAL CIRCUIT BIAS + - 25k OV DCHG2 ENABLE COMPARATOR + - 1.65V 1.0V OPEN SENSE2 OVLATCH VCCL UVLO 25k + - 25k OPEN CONTROL LOOP COMPARATOR VIDSEL VCCL S R Q OPEN CONTROL1 OV2 VCCL UV1 OV1 1.8V DYNAMIC VID2 DOWN DETECT COMPARATOR SET DOMINANT DLY OUT2 VCCL - 1.2V Figure 3 – IR3523 BLOCK DIAGRAM |
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