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IR3523MPBF Datasheet(PDF) 6 Page - International Rectifier

Part # IR3523MPBF
Description  XPHASE3TM DUAL OUTPUT CONTROL IC
PDF  37 Pages
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Manufacturer  IRF [International Rectifier]
Direct Link  http://www.irf.com
Logo IRF - International Rectifier

IR3523MPBF Datasheet(HTML) 6 Page - International Rectifier

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IR3523
Page 6 of 37
June 20, 2008
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Soft Start and Delay
Start Delay
Measure Enable to EAOUTx activation
1
2.9
3.5
ms
Start-up Time
Measure Enable activation to PGx
3
8
13
ms
OC Delay Time
V(IINx) – V(OCSETx) = 500 mV
200
650
1000
us
SS/DELx to FB Input Offset
Voltage
With FB = 0V, adjust V(SS/DEL) until
EAOUTx drives high
0.7
1.4
1.9
V
Charge Current
-30
-50
-70
µA
OC Delay Discharge Currents
Measure at charge voltage
47
µA
Fault Discharge Current
2.5
4.5
6.5
µA
Hiccup Duty Cycle
I(Fault) / I(Charge)
8
10
12
µA/µA
Charge Voltage (Output 1,2)
3.5
3.9
4.2
V
Delay Comparator Threshold
Relative to Charge Voltage, SS/DELx
rising - Note 1
70
mV
Delay Comparator Threshold
Relative to Charge Voltage, SS/DELx
falling - Note 1
135
mV
Delay Comparator Hysteresis
65
mV
VID1 Sample Delay Comparator
Threshold
2.8
3.0
3.2
V
Discharge Comp. Threshold
150
200
300
mV
Error Amplifiers
Input Offset Voltage
Measure V(FBx) – V(VDACx)). Note 2
25
oC ≤ T
J ≤ 100
oC
-1
0
1
mV
FB1 Bias Current
-5%
Vrosc(V)*100
0 /Rosc(K )
+5%
µA
FB2 Bias Current
-1
0
1
µA
DC Gain
Note 1
100
110
135
dB
Bandwidth
Note 1
20
30
40
MHz
Slew Rate
Note 1
5.5
12
20
V/µs
Sink Current
0.4
0.85
1
mA
Source Current
5.0
8.5
12.0
mA
Maximum Voltage
Measure V(VCCL) – V(EAOUTx)
500
780
950
mV
Minimum Voltage
120
250
mV
Open Control Loop Detection
Threshold
Measure V(VCCL) - V(EAOUT), Relative
to Error Amplifier maximum voltage.
125
300
600
mV
Open Control Loop Detection
Delay
Measure PHSOUT pulse numbers from
V(EAOUTx) = V(VCCL) to PGx = low.
8
Pulse
ENABLE Inputs
Threshold Increasing
1.38
1.65
1.94
V
Threshold Decreasing
0.8
0.99
1.2
V
Threshold Hysteresis
470
620
800
mV
Bias Current
0V ≤ V(x) ≤ 3.5V
-5
0
5
uA
Blanking Time
Noise Pulse < 100ns will not register an
ENABLE state change. Note 1
75
250
400
ns
PGx Outputs
Under Voltage Threshold - Voutx
Decreasing
Reference to VDAC
-365
-315
-265
mV
Under Voltage Threshold - Voutx
Increasing
Reference to VDAC
-325
-275
-225
mV
Under Voltage Threshold
Hysteresis
5
53
110
mV
Output Voltage
I(PGx) = 4mA
150
300
mV
Leakage Current
V(PGx) = 5.5V
0
10
µA
VCCL_DRV Activation Threshold
I(PGx) = 4mA, V(PGx) < 400mV,
V(VCCL) = 0
1.0
2.0
3.6
V



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