MMA6901Q datasheet(4/36 Pages) FREESCALE

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Sensors

Freescale Semiconductor

MMA690xQ

1.4.1

VCC

This pin supplies power to the device. Careful printed wiring board layout and capacitor placement is critical to ensure best

performance. An external bypass capacitor between this pin and VSS is required, as described in Section 1.5.

1.4.2

VSS

This pin is the power supply return node for the digital circuitry on the MMA690xQ device.

1.4.3

VSSA

This pin is the power supply return node for analog circuitry on the MMA690xQ device. An external bypass capacitor between

this pin and VCC is required, as described in Section 1.5.

1.4.4

CREG

This pin is connected to the internal digital circuitry power supply rail. An external filter capacitor must be connected between

this pin and VSS, as described in Section 1.5.

1.4.5

CREGA

These pins are connected in parallel to the internal analog circuitry power supply rail. One or two external filter capacitors must

be connected between these pins and VSSA, as described in Section 1.5. Two pins are provided to support redundant connection

to the printed wiring board assembly. Redundant external capacitors may be connected to these pins for maximum reliability, as

described in Section 1.5.

1.4.6

CREF

These pins are connected in parallel to an internal reference voltage node utilized by the analog circuitry. One or two external

filter capacitors must be connected between these pins and VSSA, as described shown in Section 1.5. Two pins are provided to

support redundant connection to the printed wiring board assembly. Redundant external capacitors may be connected to these

pins for maximum reliability, as described in Section 1.5.

1.4.7

VPP

This pin should be tied directly to VSS.

1.4.8

SCLK

This input pin provides the serial clock to the SPI port. The state of this pin is also used as a qualifier for externally-controlled

reset. An internal pull-down device is connected to this pin. This input may be used to initiate device reset as described in

Section 1.4.9 and Section 2.6.

1.4.9

CS/RESET

This pin functions as the chip select input for the SPI port. The state of the DIN pin during low-to-high transitions of SCLK is

latched internally and DOUT is enabled when CS is at a logic low level.

This pin may also be used to initiate a hardware reset. If CS is held low and SCLK is held high for 512

μs, the internal reset

signal is asserted. This behavior is described in Section 2.6.

An internal pull-up device is connected to this pin.

1.4.10

DOUT

This pin functions as the serial data output for the SPI port.

1.4.11

DIN

This pin functions as the serial data input to the SPI port.

1.4.12

CAP/HOLD

When this input pin is low, the SPI acceleration result registers are updated by the DSP whenever a data sample becomes

available. Upon a low-to-high transition of CAP/HOLD, the contents of the acceleration result registers are frozen. The result reg-

isters will not be updated so long as this pin remains at a logic ‘1’ level. This pin may be tied directly to VSS if the hold function is

not desired.

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