Sensors

18

Freescale Semiconductor

MMA690xQ

3.1.1.3

Device Initialization

Class: Reset

Following a reset condition, the device requires a period of time to complete initialization of the DSP and internal registers. If

multiple SPI transfers are attempted during this initialization period, the second and all subsequent transfers will result in this

status. The first transfer following reset, regardless of the state of initialization returns device reset status.

This exception condition is cleared automatically upon completion of device initialization.

3.1.1.4

Temperature Fault

Class: Critical

The internal temperature sensor value exceeds the allowable limits for the device. This exception condition may be cleared

by writing a logic ‘1’ to the CE bit in DEVCTL, provided that the temperature has returned to within the operating limits of the

device.

3.1.1.5

Unexpected Axis Selection

Class: Transient

An acceleration data request has been received with an axis specification which is not supported.

This exception condition is reported during the subsequent transfer.

3.1.1.6

Device Reset

Class: Reset

This exception condition is latched any time the device undergoes reset.

Device response will indicate the exception condition in lieu of acceleration data.The device reset exception condition must be

explicitly cleared by writing a logic ‘1’ to the CE bit in DEVCTL.

3.1.1.7

SPI Clock Fault

Class: Transient

A SPI clock fault may result from the following conditions:

• The number of rising clock edges detected while CS is asserted is not equal to the expected number for the

selected communications protocol

• SCLK is high when CS is asserted

This exception condition is reported during the subsequent transfer.

3.1.1.8

Class: Transient

This exception condition is reported during the subsequent transfer.

3.1.1.9

HOLD Condition

A HOLD condition exists when the CAP/HOLD pin is driven to a logic high level. Self-test activation is controlled through con-

figuration of ST1 and ST0 in DEVCTL.

3.1.1.10 Self-Test Activation

Class: Behavioral

The device provides two status bits in its response which will indicate a behavioral exception condition if a HOLD condition

exists or self-test is activated. As these are not error conditions, device response is otherwise unaffected. Refer to Section 3.2.1

for details regarding device response to behavioral exception conditions.

A HOLD condition exists when the CAP/HOLD pin is driven to a logic level high level. Self-test activation is controlled through

configuration of ST1 and ST0 in DEVCTL.