PIC12F752 datasheet(140/204 Pages) MICROCHIP

140 / 204 page

PIC12F752/HV752

DS41576A-page 140

Preliminary

 2011 Microchip Technology Inc.

17.3.4

BROWN-OUT RESET (BOR)

The BOREN<1:0> bits in the Configuration Word

has been added to allow control of the BOR enable for

lower current during Sleep. By selecting BOREN<1:0>

= 10, the BOR is automatically disabled in Sleep to

conserve power and enabled on wake-up. See

A brown-out occurs when VDD falls below VBOR for

greater than parameter TBOR (see Section 20.0

“Electrical Specifications”). The brown-out condition

will reset the device. This will occur regardless of VDD

slew rate. A Brown-out Reset may not occur if VDD falls

below VBOR for less than parameter TBOR.

On any Reset (Power-on, Brown-out Reset, Watchdog

timer, etc.), the chip will remain in Reset until VDD rises

above VBOR (see Figure 17-3). If enabled, the Power-

up Timer will be invoked by the Reset and keep the chip

in Reset an additional 64 ms.

If VDD drops below VBOR while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Power-up Timer will be re-initialized. Once VDD

rises above VBOR, the Power-up Timer will execute a

64 ms Reset.

Table 17-3 summarizes the registers associated with

BOR.

FIGURE 17-3:

BROWN-OUT SITUATIONS

TABLE 17-3:

SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET

Note:

The Power-up Timer is enabled by the

PWRTE bit in the Configuration Word

64 ms(1)

Vbor

VDD

Internal

Reset

Vbor

VDD

Internal

Reset

64 ms(1)

< 64 ms

64 ms(1)

Vbor

Vdd

Internal

Reset

Note 1:

64 ms delay only if PWRTE bit is programmed to ‘0’.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

PCON

—

—POR

BOR

STATUS

IRP

RP1

RP0

Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.

Shaded cells are not used by BOR.

Note 1:

Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

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