PIC12F752 datasheet(141/204 Pages) MICROCHIP

141 / 204 page

 2011 Microchip Technology Inc.

Preliminary

DS41576A-page 141

PIC12F752/HV752

17.3.5

TIME-OUT SEQUENCE

On power-up, the time-out sequence is as follows:

• PWRT time-out is invoked after POR has expired.

• OST is activated after the PWRT time-out has

expired.

The total time-out will vary based on oscillator

configuration and PWRTE bit status. For example, in EC

mode with PWRTE bit erased (PWRT disabled), there

will be no time-out at all. Figure 17-4, Figure 17-5 and

Figure 17-6 depict time-out sequences.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then,

bringing MCLR high will begin execution immediately

(see Figure 17-5). This is useful for testing purposes or

to synchronize more than one PIC12F752/HV752

device operating in parallel.

Table 17-5 shows the Reset conditions for some

special registers, while Table 17-4 shows the Reset

conditions for all the registers.

17.3.6

POWER CONTROL (PCON)

The Power Control register PCON (address 8Eh) has

two Status bits to indicate what type of Reset occurred

last.

Bit 0 is BOR (Brown-out). BOR is unknown on Power-

on Reset. It must then be set by the user and checked

on subsequent Resets to see if BOR = 0, indicating that

a Brown-out has occurred. The BOR Status bit is a

“don’t care” and is not necessarily predictable if the

brown-out circuit is disabled (BOREN<1:0> = 00 in the

Configuration Word register).

Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaffected otherwise. The user must write a

‘1’ to this bit following a Power-on Reset. On a subse-

quent Reset, if POR is ‘0’, it will indicate that a Power-

on Reset has occurred (i.e., VDD may have gone too

low).

For more information, see Section 17.3.4 “Brown-out

Reset (BOR)”.

FIGURE 17-4:

TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1

FIGURE 17-5:

TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2

TPWRT

TIOSCST

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

TPWRT

TIOSCST

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