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DS3170 DS3/E3 Single-Chip Transceiver

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PIN NAME

TYPE

PIN DESCRIPTION

TOHCLK

Transmit Overhead Clock

TOHCLK: When the port framer is configured for one of the DS3 or E3 framing

modes, this clock is used for the transmit overhead port signals TOH, TOHEN and

TOHSOF. The TOHSOF output signal is updated and the TOH and TOHEN input

signals are sampled at the same time this clock signal transitions from high to low.

The external logic is expected to sample TOHSOF signal and update the TOH and

TOHEN signals on the rising edge of this clock signal. This clock is a low frequency

clock.

This signal can be inverted.

TOHSOF

Transmit Overhead Start Of Frame

TOHSOF: When the port framer is configured for one of the DS3 or E3 framing

modes, this signal is used to mark the start of a DS3 or E3 overhead sequence on the

TOH pin. In T3 mode, the first X-bit is marked. In G.751 E3 mode, the first bit of the

FAS word is marked. In G.832 E3 mode, the first bit of the FA1 byte is marked. The

sequence starts on the same high to low transition of the TOHCLK clock that this

signal is high. This signal is updated at the same time as the TOHCLK signal

transitions high to low.

This signal can be inverted.

ROH

Receive Overhead

ROH: When the port framer is configured for one of the DS3 or E3 framing modes,

this signal outputs the value of the receive overhead bits. The ROHSOF signal marks

the start of the framing bit sequence. In T3 mode, the X-bits, P-bits, M-bits, F-bits,

and C-bits are output (Note: In M23 mode, the C-bits are extracted even though they

are marked as data at the payload interface). In G.751 E3 mode, all of the FAS, RAI,

and National Use bits are output. In G.832 E3 mode, all of the FA1, FA2, EM, TR,

MA, NR, and GC bytes are output.

This signal is updated at the same time as the ROHCLK signal transitions high to low.

This signal can be inverted.

ROHCLK

Receive Overhead Clock

ROHCLK: When the port framer is configured for one of the DS3 or E3 framing

modes, this clock is used for the receive overhead port signals ROH and ROHSOF.

The ROHSOF and ROH output signals are updated at the same time this clock signal

transitions from high to low. The external logic is expected to sample ROHSOF and

ROH signal on the rising edge of this clock signal. This clock is a low frequency clock.

This signal can be inverted.

ROHSOF

Receive Overhead Start Of Frame

ROHSOF: When the port framer is configured for one of the DS3 or E3 framing

modes this signal is used to mark the start of a DS3 or E3 overhead sequence on the

ROH pins. In T3 mode, the first X-bit is marked. In G.751 E3 mode, the first bit of the

FAS word is marked. In G.832 E3 mode, the first bit of the FA1 byte is marked. The

sequence starts on the same high to low transition of the ROHCLK clock that this

signal is high. This signal is updated at the same time as the ROHCLK signal

transitions high to low.

This signal can be inverted.

DS3/E3 Serial Data Overhead Interface

TCLKI

Transmit Line Clock Input

TCLKI: This clock is typically used for the reference clock for the TSOFI, TSER, and

TSOFO / TDEN signals but can also be used as the reference for the TPOS / TDAT

and TNEG signals. This clock is not used when the part is in loop time mode or the

CLAD clocks are used as the transmit clock source. (PORT.CR3.CLADC)

This input signal can be inverted.

DS3: 44.736 MHz +20 ppm

E3: 34.368 MHz +20 ppm

DS3170 Datasheet(PDF) 30 Page - Maxim Integrated Products

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