LPC2109 datasheet(18/46 Pages) NXP

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LPC2109_2119_2129

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Product data sheet

Rev. 7 — 14 June 2011

18 of 46

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

to trap the timer value when an input signal transitions, optionally generating an interrupt.

Multiple pins can be selected to perform a single capture or match function, providing an

application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

6.14.1 Features

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

• Timer or external event counter operation

• Four 32-bit capture channels per timer that can take a snapshot of the timer value

when an input signal transitions. A capture event may also optionally generate an

interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Four external outputs per timer corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

6.14.2 Features available in LPC2109/2119/2129/01 only

The LPC2109/2119/2129/01 can count external events on one of the capture inputs if the

external pulse lasts at least one half of the period of the PCLK. In this configuration,

unused capture lines can be selected as regular timer capture inputs, or used as external

interrupts.

• Timer can count cycles of either the peripheral clock (PCLK) or an externally supplied

clock.

• When counting cycles of an externally supplied clock, only one of the timer’s capture

inputs can be selected as the timer’s clock. The rate of such a clock is limited to

PCLK / 4. Duration of HIGH/LOW levels on the selected CAPn input cannot be

shorter than 1 / (2PCLK).

6.15 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined

amount of time.

6.15.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

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