LPC2109 datasheet(23/46 Pages) NXP

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LPC2109_2119_2129

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Product data sheet

Rev. 7 — 14 June 2011

23 of 46

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

6.18.8 APB

The APB divider determines the relationship between the processor clock (CCLK) and the

clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first

is to provide peripherals with the desired PCLK via APB so that they can operate at the

speed chosen for the ARM processor. In order to achieve this, the APB may be slowed

down to 1⁄2 to 1⁄4 of the processor clock rate. Because the APB must work properly at

power-up (and its timing cannot be altered if it does not work since the APB divider control

registers reside on the APB), the default condition at reset is for the APB to run at 1⁄4 of the

processor clock rate. The second purpose of the APB divider is to allow power savings

when an application does not require any peripherals to run at the full processor rate.

Because the APB divider is connected to the PLL output, the PLL remains active (if it was

running) during Idle mode.

6.19 Emulation and debugging

The LPC2109/2119/2129 support emulation and debugging via a JTAG serial port. A trace

port allows tracing program execution. Debugging and trace functions are multiplexed

only with GPIOs on Port 1. This means that all communication, timer and interface

peripherals residing on Port 0 are available during the development and debugging phase

as they are when the application is run in the embedded system itself.

6.19.1 EmbeddedICE

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of

the target system requires a host computer running the debugger software and an

EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote

Debug Protocol commands to the JTAG data needed to access the ARM core.

The ARM core has a Debug Communication Channel function built-in. The debug

communication channel allows a program running on the target to communicate with the

host debugger or another separate host without stopping the program flow or even

entering the debug state. The debug communication channel is accessed as a

co-processor 14 by the program running on the ARM7TDMI-S core. The debug

communication channel allows the JTAG port to be used for sending and receiving data

without affecting the normal program flow. The debug communication channel data and

control registers are mapped in to addresses in the EmbeddedICE logic.

The JTAG clock (TCK) must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG

interface to operate.

6.19.2 Embedded trace macrocell

Since the LPC2109/2119/2129 have significant amounts of on-chip memory, it is not

possible to determine how the processor core is operating simply by observing the

external pins. The ETM provides real-time trace capability for deeply embedded

processor cores. It outputs information about processor execution to the trace port.

The ETM is connected directly to the ARM core and not to the main AMBA system bus. It

compresses the trace information and exports it through a narrow trace port. An external

trace port analyzer must capture the trace information under software debugger control.

Instruction trace (or PC trace) shows the flow of execution of the processor and provides a

list of all the instructions that were executed. Instruction trace is significantly compressed

by only broadcasting branch addresses as well as a set of status signals that indicate the

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