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AD5755 Datasheet(PDF) 12 Page - Analog Devices |
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AD5755 Datasheet(HTML) 12 Page - Analog Devices |
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12 / 48 page  AD5755 Rev. 0 | Page 12 of 48 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RSET_B RSET_A REFGND REFGND AD0 AD1 SYNC SCLK SDIN SDO DVDD DGND LDAC CLEAR ALERT FAULT COMPDCDC_C IOUT_C VBOOST_C AVCC SWC GNDSWC GNDSWD SWD AVSS SWA GNDSWA GNDSWB SWB AGND VBOOST_B IOUT_B 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AD5755 TOP VIEW (Not to Scale) PIN 1 INDICATOR NOTES 1. THIS EXPOSED PADDLE SHOULD BE CONNECTED TO THE POTENTIALOF THE AVSS PIN, OR, ALTERNATIVELY, IT CAN BE LEFT ELECTRICALLY UNCONNECTED. IT IS RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. Figure 7. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 RSET_B An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_B temperature drift performance. See the Device Features section. 2 RSET_A An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_A temperature drift performance. See the Device Features section. 3 REFGND Ground Reference Point for Internal Reference. 4 REFGND Ground Reference Point for Internal Reference. 5 AD0 Address Decode for the Device Under Test (DUT) on the Board. 6 AD1 Address Decode for the DUT on the Board. 7 SYNC Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. 8 SCLK Serial Clock Input. Data is clocked into the input shift register on the rising edge of SCLK. This operates at clock speeds of up to 30 MHz. 9 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK. 10 SDO Serial Data Output. Used to clock data from the serial register in readback mode. See Figure 4 and Figure 5. 11 DVDD Digital Supply. The voltage range is from 2.7 V to 5.5 V. 12 DGND Digital Ground. 13 LDAC Load DAC, Active Low Input. This is used to update the DAC register and consequently the DAC outputs. When tied permanently low, the addressed DAC data register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the DAC output update only takes place at the falling edge of LDAC (see ). Using this mode, all analog outputs can be updated simultaneously. The Figure 3 LDAC pin must not be left unconnected. 14 CLEAR Active High, Edge Sensitive Input. Asserting this pin sets the output current and voltage to the preprogrammed clear code bit setting. Only channels enabled to be cleared are cleared. See the Device Features section for more information. When CLEAR is active, the DAC output register cannot be written to. |
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