AD5755 datasheet(33/48 Pages) AD

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AD5755

Rev. 0 | Page 33 of 48

Gain Register

The 16-bit gain register, as shown in Table 11, allows the user to

adjust the gain of each channel in steps of 1 LSB. This is done by

setting the DREG[2:0] bits to 010. It is possible to write the

same gain code to all four DAC channels at the same time by

setting the DREG[2:0] bits to 011. The gain register coding is

straight binary as shown in Table 12. The default code in the

gain register is 0xFFFF. In theory, the gain can be tuned across

the full range of the output. In practice, the maximum

recommended gain trim is about 50% of programmed range to

maintain accuracy. See the Digital Offset and Gain Control

section in the Device Features section for more information.

Offset Register

The 16-bit offset register, as shown in Table 13, allows the user to

adjust the offset of each channel by −32,768 LSBs to +32,767 LSBs

in steps of 1 LSB. This is done by setting the DREG[2:0] bits to

100. It is possible to write the same offset code to all four DAC

channels at the same time by setting the DREG[2:0] bits to 101.

The offset register coding is straight binary as shown in Table 14.

The default code in the offset register is 0x8000, which results in

zero offset programmed to the output. See the Digital Offset

and Gain Control section in the Device Features section for

more information.

Clear Code Register

The 16-bit clear code register allows the user to set the clear

value of each channel as shown in Table 15. It is possible, via

software, to enable or disable on a per channel basis which

channels are cleared when the CLEAR pin is activated. The

default clear code is 0x0000. See the Asynchronous Clear

section in the Device Features section for more information.

Table 11. Programming the Gain Register

R/W

DUT_AD1

DUT_AD0

DREG2

DREG1

DREG0

DAC_AD1

DAC_AD0

D15 to D0

Device address

DAC channel address

Gain adjustment

Table 12. Gain Register

Gain Adjustment

G15

G14

G13

G12 to G4

+65,535 LSBs

+65,534 LSBs

…

1 LSB

0 LSBs

Table 13. Programming the Offset Register

R/W

DUT_AD1

DUT_AD0

DREG2

DREG1

DREG0

DAC_AD1

DAC_AD0

D15 to D0

Device address

DAC channel address

Offset adjustment

Table 14. Offset Register Options

Offset Adjustment

OF15

OF14

OF13

OF12 to OF4

OF3

OF2

OF1

OF0

+32,767 LSBs

+32,766 LSBs

…

No Adjustment (Default)

…

−32,767 LSBs

−32,768 LSBs

Table 15. Programming the Clear Code Register

R/W

DUT_AD1

DUT_AD0

DREG2

DREG1

DREG0

DAC_AD1

DAC_AD0

D15 to D0

Device address

DAC channel address

Clear code

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