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LPC1850 Datasheet(PDF) 55 Page - NXP Semiconductors

Part # LPC1850
Description  32-bit ARM Cortex-M3 MCU; up to 200 kB SRAM; Ethernet, two High-speed USB, LCD, and external memory controller
PDF  142 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC1850 Datasheet(HTML) 55 Page - NXP Semiconductors

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LPC1850_30_20_10
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Preliminary data sheet
Rev. 2.2 — 9 September 2011
55 of 142
NXP Semiconductors
LPC1850/30/20/10
32-bit ARM Cortex-M3 microcontroller
Clock pins
CLK0
N5
x
K3
x
45
31
[5]
O;
PU
O
EMC_CLK0 — SDRAM clock 0.
O
CLKOUT — Clock output pin.
-
R — Function reserved.
-
R — Function reserved.
I/O
SD_CLK — SD/MMC card clock.
O
EMC_CLK01 — SDRAM clock 0 and clock 1
combined.
I/O
SSP1_SCK — Serial clock for SSP1.
I
ENET_TX_CLK (ENET_REF_CLK) — Ethernet
Transmit Clock (MII interface) or Ethernet Reference
Clock (RMII interface).
CLK1
T10
x
-
-
-
-
[5]
O;
PU
O
EMC_CLK1 — SDRAM clock 1.
O
CLKOUT — Clock output pin.
-
R — Function reserved.
-
R — Function reserved.
-
R — Function reserved.
O
CGU_OUT0 — CGU spare clock output 0.
-
R — Function reserved.
O
I2S1_TX_MCLK — I2S1 transmit master clock.
CLK2
D14
x
K6
x
99
68
[5]
O;
PU
O
EMC_CLK3 — SDRAM clock 3.
O
CLKOUT — Clock output pin.
-
R — Function reserved.
-
R — Function reserved.
I/O
SD_CLK — SD/MMC card clock.
O
EMC_CLK23 — SDRAM clock 2 and clock 3
combined.
O
I2S0_TX_MCLK — I2S transmit master clock.
I/O
I2S1_RX_SCK — Receive Clock. It is driven by the
master and received by the slave. Corresponds to the
signal SCK in the I2S-bus specification.
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
Description



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