LPC1850 datasheet(80/142 Pages) NXP

80 / 142 page

LPC1850_30_20_10

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Preliminary data sheet

Rev. 2.2 — 9 September 2011

80 of 142

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

• Ethernet mode

• Memory mapping

• Timer/USART inputs

• Enabling the USB controllers

In addition, the CREG block contains the part identification and part configuration

information.

7.18.2 System Control Unit (SCU)

The system control unit determines the function and electrical mode of the digital pins. By

default function 0 is selected for all pins with pull-up enabled.

Analog I/Os for the ADCs and the DAC as well as most USB pins are on separate pads

and are not controlled through the SCU.

7.18.3 Clock Generation Unit (CGU)

The Clock Generator Unit (CGU) generates several base clocks. The base clocks can be

unrelated in frequency and phase and can have different clock sources within the CGU.

One CGU base clock is routed to the CLKOUT pins.

Multiple branch clocks are derived from each base clock. The branch clocks offer very

flexible control for power-management purposes. All branch clocks are outputs of one of

two Clock Control Units (CCUs) and can be controlled independently. Branch clocks

derived from the same base clock are synchronous in frequency and phase.

7.18.4 Internal RC oscillator (IRC)

The IRC is used as the clock source for the WWDT and/or as the clock that drives the

PLLs and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is

trimmed to 1 % accuracy over the entire voltage and temperature range.

Upon power-up or any chip reset, the LPC1850/30/20/10 use the IRC as the clock source.

Software may later switch to one of the other available clock sources.

7.18.5 PLL0USB (for USB0)

PLL0 is a dedicated PLL for the USB0 High-speed controller.

PLL0 accepts an input clock frequency from an external oscillator in the range of 14 kHz

to 25 MHz. The input frequency is multiplied up to a high frequency with a Current

Controlled Oscillator (CCO). The CCO operates in the range of 4.3 MHz to 550 MHz.

7.18.6 PLL0AUDIO (for audio)

The audio PLL PLL0AUDIO is a general purpose PLL with a very small step size. This

PLL accepts an input clock frequency derived from an external oscillator or internal IRC.

The input frequency is multiplied up to a high frequency with a Current Controlled

Oscillator (CCO). A sigma-delta converter modulates the PLL divider ratios to obtain the

desired output frequency. The output frequency can be set to 32

f

s, 64fs, 128  fs,

256

 f

s, 384  fs and the sampling frequency fs can range from 16 kHz to 192 kHz (16,

22.05, 32, 44.1, 48, 96,192) kHz.

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