LPC1850 datasheet(74/142 Pages) NXP

74 / 142 page

LPC1850_30_20_10

All information provided in this document is subject to legal disclaimers.

Preliminary data sheet

Rev. 2.2 — 9 September 2011

74 of 142

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

7.14.2.1

Features

• Maximum UART data bit rate of <tbd> MBit/s.

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Auto baud capabilities and FIFO control mechanism that enables software flow

control implementation.

• Support for RS-485/9-bit/EIA-485 mode.

• USART3 includes an IrDA mode to support infrared communication.

• All USARTs have DMA support.

• Support for synchronous mode.

• Smart card mode conforming to ISO7816 specification

7.14.3 SSP serial I/O controller

Remark: The LPC1850/30/20/10 contain two SSP controllers.

The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. Only a single master and a single

slave can communicate on the bus during a given data transfer. The SSP supports full

duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the

slave and from the slave to the master. In practice, often only one of these data flows

carries meaningful data.

7.14.3.1

Features

• Maximum SSP speed of <tbd> Mbit/s (master) or <tbd> Mbit/s (slave)

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

• DMA transfers supported by GPDMA

7.14.4 I2C-bus interface

Remark: The LPC1850/30/20/10 each contain two I2C-bus controllers.

The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line

(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be

controlled by more than one bus master connected to it.

LPC1850 Datasheet(PDF) 74 Page - NXP Semiconductors

LPC1850 Datasheet(HTML) 74 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL