LPC1850 datasheet(56/142 Pages) NXP

56 / 142 page

LPC1850_30_20_10

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Preliminary data sheet

Rev. 2.2 — 9 September 2011

56 of 142

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

CLK3

P12

[5]

EMC_CLK2 — SDRAM clock 2.

CLKOUT — Clock output pin.

R — Function reserved.

CGU_OUT1 — CGU spare clock output 1.

R — Function reserved.

I/O

I2S1_RX_SCK — Receive Clock. It is driven by the

master and received by the slave. Corresponds to the

signal SCK in the I2S-bus specification.

Debug pins

DBGEN

[3]

I; PD I

JTAG interface control signal. Also used for boundary

scan.

TCK/SWDCLK

[3]

I; F

Test Clock for JTAG interface (default) or Serial Wire

(SW) clock.

TRST

[3]

I; PU I

Test Reset for JTAG interface.

TMS/SWDIO

[3]

I; PU I

Test Mode Select for JTAG interface (default) or SW

debug data input/output.

TDO/SWO

[3]

Test Data Out for JTAG interface (default) or SW trace

output.

TDI

[3]

I; PU I

Test Data In for JTAG interface.

USB0 pins

USB0_DP

[7]

I/O

USB0 bidirectional D+ line.

USB0_DM

[7]

I/O

USB0 bidirectional D

 line.

USB0_VBUS

[7]

I/O

VBUS pin (power on USB cable).

USB0_ID

[8]

Indicates to the transceiver whether connected to an

A-device (LOW) or a B-device (HIGH).

USB0_RREF

[8]

12.0 k

 (accuracy 1 %) on-board resistor to ground for

current reference.

USB1 pins

USB1_DP

F12

[9]

I/O

USB1 bidirectional D+ line.

USB1_DM

G12

E10

[9]

I/O

USB1 bidirectional D

 line.

I2C-bus pins

I2C0_SCL

L15

[10]

I; F

I/O

I2C clock input/output. Open-drain output (for I2C-bus

compliance).

I2C0_SDA

L16

[10]

I; F

I/O

I2C data input/output. Open-drain output (for I2C-bus

compliance).

Table 3.

Pin description …continued

LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.

Symbol

Description

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