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STM32F407IG Datasheet(PDF) 108 Page - STMicroelectronics |
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STM32F407IG Datasheet(HTML) 108 Page - STMicroelectronics |
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108 / 154 page ![]() Electrical characteristics STM32F405xx, STM32F407xx 108/154 Doc ID 022152 Rev 1 tS (5) Sampling time fADC = 36 MHz 0.100 - 16 µs 3 - 416 1/fADC tSTAB (5) Power-up time - 2 3 µs tCONV (5) Total conversion time (including sampling time) fADC = 36 MHz 12-bit resolution 0.416 - 12.95 µs fADC = 36 MHz 10-bit resolution 0.360 - 12.89 µs fADC = 36 MHz 8-bit resolution 0.305 - 12.84 µs fADC = 36 MHz 6-bit resolution 0.250 - 12.79 µs 9 to 492 (tS for sampling +n-bit resolution for successive approximation) 1/fADC fS (5) Sampling rate (fADC = 36 MHz) 12-bit resolution Single ADC -- 2.4 Msps 12-bit resolution Interleave Dual ADC mode -- 4.8 Msps 12-bit resolution Interleave Triple ADC mode -- 7.2 Msps IVREF+ (5) ADC VREF DC current consumption in conversion mode fADC = 36 MHz 3 sampling time 12-bit resolution - 300 500 µA fADC = 36 MHz 480 sampling time 12-bit resolution -- TBD µA IDDA (5) ADC VDDA DC current consumption in conversion mode fADC = 36 MHz 3 sampling time 12-bit resolution -1.6 1.8 mA fADC = 36 MHz 480 sampling time 12-bit resolution -- TBD 1. TBD stands for “to be defined”. 2. If PDR_ON is set to VSS, this value can be lowered to 1.7 V when the device operates in a reduced temperature range (0 to 70 °C). 3. VDDA -VREF+ < 1.2 V. 4. It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V. 5. Based on characterization, not tested in production. 6. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 7. RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V. 8. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 64. Table 64. ADC characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit |
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