LPC1850 datasheet(62/157 Pages) PHILIPS

62 / 157 page

LPC1850_30_20_10

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Preliminary data sheet

Rev. 3 — 6 December 2011

62 of 157

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

CLK2

D14

141

[5]

EMC_CLK3 — SDRAM clock 3.

CLKOUT — Clock output pin.

R — Function reserved.

I/O

SD_CLK — SD/MMC card clock.

EMC_CLK23 — SDRAM clock 2 and clock 3

combined.

I2S0_TX_MCLK — I2S transmit master clock.

I/O

I2S1_RX_SCK — Receive Clock. It is driven by the

master and received by the slave. Corresponds to

the signal SCK in the I2S-bus specification.

CLK3

P12

[5]

EMC_CLK2 — SDRAM clock 2.

CLKOUT — Clock output pin.

R — Function reserved.

CGU_OUT1 — CGU spare clock output 1.

R — Function reserved.

I/O

I2S1_RX_SCK — Receive Clock. It is driven by the

master and received by the slave. Corresponds to

the signal SCK in the I2S-bus specification.

Debug pins

DBGEN

[3]

JTAG interface control signal. Also used for boundary

scan.

TCK/SWDCLK

[3]

I; F

Test Clock for JTAG interface (default) or Serial Wire

(SW) clock.

TRST

B442

2919

[3]

I; PU I

Test Reset for JTAG interface.

TMS/SWDIO

[3]

I; PU I

Test Mode Select for JTAG interface (default) or SW

debug data input/output.

TDO/SWO

[3]

Test Data Out for JTAG interface (default) or SW

trace output.

TDI

[3]

I; PU I

Test Data In for JTAG interface.

USB0 pins

USB0_DP

[7]

I/O

USB0 bidirectional D+ line.

USB0_DM

[7]

I/O

USB0 bidirectional D

 line.

USB0_VBUS

[7]

[8]

I/O

VBUS pin (power on USB cable). This pin includes

an internal pull-down resistor of 64 k

 (typical) 

16 k

.

Table 3.

Pin description …continued

LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.

Symbol

Description

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