LPC1850 datasheet(66/157 Pages) PHILIPS

66 / 157 page

LPC1850_30_20_10

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Preliminary data sheet

Rev. 3 — 6 December 2011

66 of 157

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

[3]

5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDD(IO) present; if VDD(IO) not present, do not exceed 3.3 V); provides digital I/O

functions with TTL levels and hysteresis; normal drive strength (see Figure 39).

[4]

5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDD(IO) present; if VDD(IO) not present, do not exceed 3.3 V); provides digital I/O

functions with TTL levels, and hysteresis; high drive strength (see Figure 39).

[5]

5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDD(IO) present; if VDD(IO) not present, do not exceed 3.3 V); provides high-speed

digital I/O functions with TTL levels and hysteresis (see Figure 39).

[6]

5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output (5 V tolerant if VDD(IO) present;

if VDD(IO) not present, do not exceed 3.3 V). When configured as a ADC input or DAC output, the pin is not 5 V tolerant and the digital

section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin’s SFSP

[7]

5 V tolerant transparent analog pad.

[8]

For maximum load CL = 6.5 F and maximum pull-down resistance Rpd = 80 k, the VBUS signal takes about 2 s to fall from VBUS =

5 V to VBUS = 0.2 V when it is no longer driven.

[9]

Transparent analog pad. Not 5 V tolerant.

[10] Pad provides USB functions. 5 V tolerant if VDD(IO) present; if VDD(IO) not present do not exceed 3.3 V. It is designed in accordance with

the USB specification, revision 2.0 (Full-speed and Low-speed mode only).

[11] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus Fast Mode Plus specification. This pad requires an external pull-up to

provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.

[12] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output with weak pull-up resistor and hysteresis

(see Figure 40).

[13] On the TFBGA100 and LQFP208 packages, VPP is internally connected to VDDIO.

[14] On the LQFP144/208 packages, VSSIO and VSS are connected to a common ground plane.

[15] On the TFBGA100 and LQFP100/208 packages, VSS is internally connected to VSSIO.

LPC1850 Datasheet(PDF) 66 Page - NXP Semiconductors