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NVT2002 Datasheet(PDF) 8 Page - NXP Semiconductors |
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NVT2002 Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 23 page ![]() NVT2001_NVT2002 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 26 October 2011 8 of 23 NXP Semiconductors NVT2001; NVT2002 Bidirectional voltage level translator 7.3.1 Maximum frequency calculation The maximum frequency is totally dependent upon the specifics of the application and the device can operate > 33 MHz. Basically, the NVT20xx behaves like a wire with the additional characteristics of transistor device physics and should be capable of performing at higher frequencies if used correctly. Here are some guidelines to follow that will help maximize the performance of the device: • Keep trace length to a minimum by placing the NVT20xx close to the processor. • The trace length should have a time of flight less than half of the transition time to reduce ringing and reflections. • The faster the edge of the signal, the higher the chance for ringing. • The higher the drive strength (up to 15 mA), the higher the frequency the device can use. In a 3.3 V to 1.8 V direction level shift, if the 3.3 V side is being driven by a totem pole type driver no pull-up resistor is needed on the 3.3 V side. The capacitance and line length of concern is on the 1.8 V side since it is driven through the ON resistance of the NVT20xx. If the line length on the 1.8 V side is long enough there can be a reflection at the chip/terminating end of the wire when the transition time is shorter than the time of flight of the wire because the NVT20xx looks like a high-impedance compared to the wire. If the wire is not too long and the lumped capacitance is not excessive the signal will only be slightly degraded by the series resistance added by passing through the NVT20xx. If the lumped capacitance is large the rise time will deteriorate, the fall time is much less affected and if the rise time is slowed down too much the duty cycle of the clock will be degraded and at some point the clock will no longer be useful. So the principle design consideration is to minimize the wire length and the capacitance on the 1.8 V side for the clock path. A pull-up resistor on the 1.8 V side can also be used to trade a slower fall time for a faster rise time and can also reduce the overshoot in some cases. 7.3.1.1 Example maximum frequency Question — We need to make the PLL area of a new line card backwards compatible and need to need to convert one GTL signal to LVTTL, invert it, and convert it back to GTL. The signal we want to convert is random in nature but will mostly be around 19 MHz with very long periods of inactivity where either a HIGH or LOW state will be maintained. The traces are 1 or 2 inches long with trace capacitance of about 2 pF per inch. Answer — The frequency of the NVT20xx is limited by the capacitance of the part, the capacitance of the traces and the pull-up resistors used. The limiting case is probably the LOW-to-HIGH transition in the GTL to LVTTL direction, and there the use of the lowest acceptable resistor values will minimize the rise time delay. Assuming 50 pF capacitance and 220 resistance, the RC time constant is 11 ns (50 pF 220 ). With 19 MHz corresponding to 50 ns period the NVT20xx will support this application. |
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