NVT2002 datasheet(12/23 Pages) PHILIPS

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NVT2001_NVT2002

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Product data sheet

Rev. 2 — 26 October 2011

12 of 23

NXP Semiconductors

NVT2001; NVT2002

Bidirectional voltage level translator

12. Performance curves

tPLH up-translation is typically dominated by the RC time constant, i.e.,

CL(tot)  RPU =50pF  197  = 9.85 ns, but the Ron  CL(tot) =50pF  5  =0.250 ns.

tPHL is typically dominated by the external pull-down driver + Ron, which is typically small

compared to the tPLH in an up-translation case.

Enable/disable times are dominated by the RC time constant on the EN pin since the

transistor turn off is on the order of ns, but the enable RC is on the order of ms.

Fall time is dominated by the external pull-down driver with only a slight Ron addition.

Rise time is dominated by the RPU  CL.

Skew time within the part is virtually non-existent, dominated by the difference in bond

wire lengths, which is typically small compared to the board-level routing differences.

Maximum data rate is dominated by the system capacitance and pull-up resistors.

(1) VI(EN) = 1.5 V; IO =64mA; VI =0V.

(2) VI(EN) = 4.5 V; IO =15mA; VI =2.4 V.

(3) VI(EN) = 2.3 V; IO =64mA; VI =0V.

(4) VI(EN) = 3.0 V; IO =64mA; VI =0V.

(5) VI(EN) = 4.5 V; IO =64mA; VI =0V.

Fig 13. Typical capacitance versus propagation delay

C (pF)

100

002aaf349

0.4

0.2

0.6

0.8

tPD

(ns)

(1)

(2)

(3)

(5)

(4)

NVT2002 Datasheet(PDF) 12 Page - NXP Semiconductors