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AM3359 Datasheet(PDF) 19 Page - Texas Instruments |
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AM3359 Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 195 page  AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717B – OCTOBER 2011 – REVISED JANUARY 2012 Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) BALL RESET BUFFER PULLUP ZCE BALL ZCZ BALL TYPE BALL RESET RESET REL. ZCE POWER / HYS PIN NAME [2] SIGNAL NAME [3] MODE [4] REL. STATE STRENGTH /DOWN TYPE I/O CELL [13] NUMBER [1] NUMBER [1] [5] STATE [6] MODE [8] ZCZ POWER [9] [10] [7] (mA) [11] [12] B8 B6 AIN0 AIN0 0 A (13) Z Z 0 VDDA_ADC / NA 50 NA Analog VDDA_ADC A11 C7 AIN1 AIN1 0 A (12) Z Z 0 VDDA_ADC / NA 50 NA Analog VDDA_ADC A8 B7 AIN2 AIN2 0 A (12) Z Z 0 VDDA_ADC / NA 50 NA Analog VDDA_ADC B11 A7 AIN3 AIN3 0 A (11) Z Z 0 VDDA_ADC / NA 50 NA Analog VDDA_ADC C8 C8 AIN4 AIN4 0 A (11) Z Z 0 VDDA_ADC / NA 50 NA Analog VDDA_ADC B12 B8 AIN5 AIN5 0 A Z Z 0 VDDA_ADC / NA NA NA Analog VDDA_ADC A10 A8 AIN6 AIN6 0 A Z Z 0 VDDA_ADC / NA NA NA Analog VDDA_ADC A12 C9 AIN7 AIN7 0 A Z Z 0 VDDA_ADC / NA NA NA Analog VDDA_ADC C13 C10 CAP_VBB_MPU CAP_VBB_MPU NA A D6 D6 CAP_VDD_RTC CAP_VDD_RTC NA A B10 D9 CAP_VDD_SRAM_CORE CAP_VDD_SRAM_CORE NA A D13 D11 CAP_VDD_SRAM_MPU CAP_VDD_SRAM_MPU NA A F3 F3 DDR_A0 ddr_a0 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL J2 H1 DDR_A1 ddr_a1 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL D1 E4 DDR_A2 ddr_a2 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL B3 C3 DDR_A3 ddr_a3 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL E5 C2 DDR_A4 ddr_a4 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL A2 B1 DDR_A5 ddr_a5 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL B1 D5 DDR_A6 ddr_a6 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL D2 E2 DDR_A7 ddr_a7 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL C3 D4 DDR_A8 ddr_a8 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL B2 C1 DDR_A9 ddr_a9 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL E2 F4 DDR_A10 ddr_a10 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL G4 F2 DDR_A11 ddr_a11 0 O H 1 0 VDDS_DDR / NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL Copyright © 2011–2012, Texas Instruments Incorporated Terminal Description 19 Submit Documentation Feedback Product Folder Link(s): AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 |
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