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AM3359 Datasheet(PDF) 21 Page - Texas Instruments

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Part # AM3359
Description  AM335x ARM짰 Cortex??A8 Microprocessors (MPUs)
PDF  195 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM3359 Datasheet(HTML) 21 Page - Texas Instruments

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AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com
SPRS717B
– OCTOBER 2011 – REVISED JANUARY 2012
Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
BUFFER
PULLUP
ZCE BALL
ZCZ BALL
TYPE BALL RESET
RESET REL.
ZCE POWER /
HYS
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
REL. STATE
STRENGTH
/DOWN TYPE
I/O CELL [13]
NUMBER [1] NUMBER [1]
[5]
STATE [6]
MODE [8]
ZCZ POWER [9]
[10]
[7]
(mA) [11]
[12]
M4
K3
DDR_D11
ddr_d11
0
I/O
L
Z
0
VDDS_DDR /
Yes
8
PU/PD
LVCMOS/SSTL/
VDDS_DDR
HSTL
M2
K4
DDR_D12
ddr_d12
0
I/O
L
Z
0
VDDS_DDR /
Yes
8
PU/PD
LVCMOS/SSTL/
VDDS_DDR
HSTL
M1
L3
DDR_D13
ddr_d13
0
I/O
L
Z
0
VDDS_DDR /
Yes
8
PU/PD
LVCMOS/SSTL/
VDDS_DDR
HSTL
N2
L4
DDR_D14
ddr_d14
0
I/O
L
Z
0
VDDS_DDR /
Yes
8
PU/PD
LVCMOS/SSTL/
VDDS_DDR
HSTL
N1
M1
DDR_D15
ddr_d15
0
I/O
L
Z
0
VDDS_DDR /
Yes
8
PU/PD
LVCMOS/SSTL/
VDDS_DDR
HSTL
N3
M2
DDR_DQM0
ddr_dqm0
0
O
H
1
0
VDDS_DDR /
NA
8
PU/PD
LVCMOS/SSTL/
VDDS_DDR
HSTL
K3
J2
DDR_DQM1
ddr_dqm1
0
O
H
1
0
VDDS_DDR /
NA
8
PU/PD
LVCMOS/SSTL/
VDDS_DDR
HSTL
R1
P1
DDR_DQS0
ddr_dqs0
0
I/O
L
Z
0
VDDS_DDR /
Yes
8
PU/PD
LVCMOS/SSTL/
VDDS_DDR
HSTL
L1
L1
DDR_DQS1
ddr_dqs1
0
I/O
L
Z
0
VDDS_DDR /
Yes
8
PU/PD
LVCMOS/SSTL/
VDDS_DDR
HSTL
R2
P2
DDR_DQSn0
ddr_dqsn0
0
I/O
L
Z
0
VDDS_DDR /
Yes
8
PU/PD
LVCMOS/SSTL/
VDDS_DDR
HSTL
L2
L2
DDR_DQSn1
ddr_dqsn1
0
I/O
L
Z
0
VDDS_DDR /
Yes
8
PU/PD
LVCMOS/SSTL/
VDDS_DDR
HSTL
G1
G1
DDR_ODT
ddr_odt
0
O
L
0
0
VDDS_DDR /
NA
8
PU/PD
LVCMOS/SSTL/
VDDS_DDR
HSTL
F2
G4
DDR_RASn
ddr_rasn
0
O
H
1
0
VDDS_DDR /
NA
8
PU/PD
LVCMOS/SSTL/
VDDS_DDR
HSTL
G2
G2
DDR_RESETn
ddr_resetn
0
O
L
0
0
VDDS_DDR /
NA
8
PU/PD
LVCMOS/SSTL/
VDDS_DDR
HSTL
H4
J4
DDR_VREF
ddr_vref
0
AP
(9)
NA
NA
NA
VDDS_DDR /
NA
NA
NA
Analog
VDDS_DDR
J1
J3
DDR_VTP
ddr_vtp
0
I
(10)
NA
NA
NA
VDDS_DDR /
NA
NA
NA
Analog
VDDS_DDR
A4
B2
DDR_WEn
ddr_wen
0
O
H
1
0
VDDS_DDR /
NA
8
PU/PD
LVCMOS/SSTL/
VDDS_DDR
HSTL
E18
C18
ECAP0_IN_PWM0_OUT
eCAP0_in_PWM0_out
0
I/O
Z
L
7
VDDSHV6 /
Yes
4
PU/PD
LVCMOS
VDDSHV6
uart3_txd
1
O
spi1_cs1
2
I/O
pr1_ecap0_ecap_capin_apwm_o
3
I/O
spi1_sclk
4
I/O
mmc0_sdwp
5
I
xdma_event_intr2
6
I
gpio0_7
7
I/O
A15
C14
EMU0
EMU0
0
I/O
H
H
0
VDDSHV6 /
Yes
6
PU/PD
LVCMOS
VDDSHV6
gpio3_7
7
I/O
Copyright
© 2011–2012, Texas Instruments Incorporated
Terminal Description
21
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Product Folder Link(s): AM3359 AM3358 AM3357 AM3356 AM3354 AM3352



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