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AM3359 Datasheet(PDF) 3 Page - Texas Instruments |
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AM3359 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 195 page  AM3359, AM3358, AM3357 AM3356, AM3354, AM3352 www.ti.com SPRS717B – OCTOBER 2011 – REVISED JANUARY 2012 • Supports Time Division Multiplexing Balancing and Power Management (TDM), Inter-IC Sound (I2S), and similar • Advanced Geometry DMA Driven Formats Operation for Minimum CPU Interaction • Supports Digital Audio Interface • Programmable High-Quality Image Transmission (SPDIF, IEC60958-1, and Anti-Aliasing AES-3 Formats) • Fully Virtualized Memory Addressing for • FIFO Buffers for Transmit and Receive OS Operation in a Unified Memory (256 bytes) Architecture – Up to Six UARTs – LCD Controller • All UARTs Support IrDA and CIR Modes • Up to 24-Bits Data Output; 8-Bits per • All UARTs Support RTS and CTS Flow Pixel (RGB) Control • Up to WXGA (1366x768) Resolution • UART1 Supports Full Modem control • Integrated LCD Interface Display Driver – Up to Two Master/Slave McSPI Serial (LIDD) Controller Interfaces • Integrated Raster Controller • Up to Two Chip Selects • Integrated DMA Engine to Pull Data from • Up to 48 MHz the External Frame Buffer without Burdening the Processor via Interrupts or – Up to Three MMC/SD/SDIO Ports a Firmware Timer • 1-Bit, 4-Bit and 8-Bit MMC/SD/SDIO • 512-Word Deep Internal FIFO Modes • Supported Display Types: • MMCSD0 has dedicated Power Rail for 1.8-V or 3.3-V Operation – Character Displays - Uses LCD Interface Display Driver (LIDD) • Up to 48-MHz Data Transfer Rate Controller to Program these Displays • Supports Card Detect and Write Protect – Passive Matrix LCD Displays - Uses • Complies with MMC4.3 and SD/SDIO 2.0 LCD Raster Display Controller to Specifications Provide Timing and Data for Constant – Up to Three I2C Master/Slave Interfaces Graphics Refresh to a Passive Display • Standard Mode (up to 100 kHz) – Active Matrix LCD Displays - Uses • Fast Mode (up to 400 kHz) External Frame Buffer Space and the – Up to Four Banks of General-Purpose IO Internal DMA Engine to Drive (GPIO) Streaming Data to the Panel. Maximum • 32 GPIOs per Bank (Multiplexed with Resolution is WXGA (1366x768) at Other Functional Pins) 60-Hz Refresh Rate • GPIOs Can be Used as Interrupt Inputs – 12-Bit Successive Approximation Register (Up to Two Interrupt Inputs per Bank) (SAR) ADC – Up to Three External DMA Event Inputs That • 100K Samples per Second Can Also be Used as Interrupt Inputs • Input Can be Selected from any of the – Eight 32-Bit General-Purpose Timers Eight Analog Inputs Multiplexed Through an 8:1 analog Switch • DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks • Can be Configured to Operate as a 4-wire, 5-wire, or 8-wire Resistive Touch Screen • DMTIMER4 - DMTIMER7 are Pinned Out Controller (TSC) Interface – One Watchdog Timer – Up to Three 32-Bit Enhanced Capture – SGX530 3D Graphics Engine Modules (eCAP) • Tile-Based Architecture Delivering Up to • Configurable as Three Capture Inputs or 20 MPloy/sec Three Auxiliary PWM Outputs • Universal Scalable Shader Engine is a – Up to Three Enhanced High-Resolution PWM Multi-Threaded Engine Incorporating Modules (eHRPWM) Pixel and Vertex Shader Functionality • Dedicated 16-Bit Time-Base Counter with • Advanced Shader Feature Set in Excess Time and Frequency Controls of Microsoft VS3.0, PS3.0 and OGL2.0 • Configurable as Six Single-Ended, Six • Industry Standard API Support of Dual-Edge Symmetric, or Three Direct3D Mobile, OGL-ES 1.1 and 2.0, Dual-Edge Asymmetric Outputs OpenVG 1.0, and OpenMax – Up to Three 32-Bit Enhanced Quadrature • Fine-Grained Task Switching, Load Pulse Encoder (eQPE) Modules Copyright © 2011–2012, Texas Instruments Incorporated Device Summary 3 Submit Documentation Feedback Product Folder Link(s): AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 |
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