MAX7370 datasheet(16/37 Pages) MAXIM

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MAX7370

8 x 8 Key-Switch Controller and LED Driver/GPIOs

with I2C Interface and High Level of ESD Protection

Slave Addresses

The device has two 7-bit long slave addresses. The bit

following a 7-bit slave address is the R/W bit, which is

low for a write command and high for a read command.

The first 4 bits (MSBs) of the device slave addresses

are always 0111. Slave address bits A[3:1] correspond,

by the matrix in Table 3, to the states of the device

address input pin AD0, and A0 corresponds to the

R/W bit (Figure 5). The AD0 input can be connected

to any of four signals: GND, VCC, SDA, or SCL, giv-

ing four possible slave-address pairs, allowing up to

four devices to share the same bus. Because SDA and

SCL are dynamic signals, care must be taken to ensure

that AD0 transitions no sooner than the signals on

SDA and SCL.

The device monitors the bus continuously, waiting for a

START condition, followed by its slave address. When

the device recognizes its slave address, it acknowledges

and is then ready for continued communication.

Bus Timeout

The device features a 20ms (min) bus timeout on the

two-wire serial interface, largely to prevent the device

from holding the SDA I/O low during a read transac-

tion should the SCL lock up for any reason before a

serial transaction is completed. Bus timeout operates by

causing the device to internally terminate a serial trans-

action, either read or write, if the time between adjacent

edges on SCL exceeds 20ms. After a bus timeout, the

device waits for a valid START condition before respond-

ing to a consecutive transmission. This feature can be

enabled or disabled under user control by writing to the

configuration register.

Message Format for Writing

the Keyscan Controller

A write to the device comprises the transmission of the slave

address with the R/W bit set to zero, followed by at least one

byte of information. The first byte of information is the com-

mand byte. The command byte determines which register

of the device is to be written by the next byte, if received.

If a STOP condition is detected after the command byte

is received, the device takes no further action (Figure 6)

beyond storing the command byte.

Any bytes received after the command byte are data bytes.

The first data byte goes into the internal register of the

device selected by the command byte (Figure 7).

If multiple data bytes are transmitted before a STOP condi-

tion is detected, these bytes are generally stored in sub-

sequent internal registers of the device, because the com-

mand-byte address generally autoincrements (Table 4).

Figure 4. Acknowledge

Figure 5. Slave Address

Table 3. Two-Wire Interface Address Map

AD0

DEVICE ADDRESS

GND

R/W

VCC

SDA

SCL

SDA BY

TRANSMITTER

CLOCK PULSE FOR

ACKNOWLEDGE

START

CONDITION

SDA BY

RECEIVER

SDA

SCL

1A3A2A1

MSB

LSB

ACK

R/W

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