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MAX7370 Datasheet(PDF) 4 Page - Maxim Integrated Products

Part # MAX7370
Description  8 x 8 Key-Switch Controller and LED Driver/GPIOs
PDF  37 Pages
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX7370 Datasheet(HTML) 4 Page - Maxim Integrated Products

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����������������������������������������������������������������� Maxim Integrated Products 4
MAX7370
8 x 8 Key-Switch Controller and LED Driver/GPIOs
with I2C Interface and High Level of ESD Protection
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 1.62V to 3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25NC.) (Notes 2, 3)
Note 2: All parameters are tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 3: All digital inputs at VCC or GND.
Note 4: Guaranteed by design.
Note 5: CB = total capacitance of one bus line in pF. tR and tF measured between 0.8V and 2.1V.
Note 6: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 7: ISINK = 6mA. CB = total capacitance of one bus line in pF. tR and tF measured between 0.8V and 2.1V.
Note 8: Input filters on the SDA, SCL, and AD0 inputs suppress noise spikes less than 50ns.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I2C TIMING SPECIFICATIONS
SCL Serial-Clock Frequency
fSCL
Bus timeout enabled
0.05
400
kHz
Bus timeout disabled
0
400
Bus Free Time Between a STOP and
START Condition
tBUF
1.3
F
s
Hold Time (Repeated) START Condition
tHD, STA
0.6
F
s
Repeated START Condition Setup Time
tSU, STA
0.6
F
s
STOP Condition Setup Time
tSU, STO
0.6
F
s
Data Hold Time
tHD, DAT (Note 6)
0.9
F
s
Data Setup Time
tSU, DAT
100
ns
SCL Clock Low Period
tLOW
1.3
F
s
SCL Clock High Period
tHIGH
0.7
F
s
Rise Time of Both SDA and SCL
Signals, Receiving
tR
(Notes 4, 5)
20 +
0.1CB
300
ns
Fall Time of Both SDA and SCL Signals,
Receiving
tF
(Notes 4, 5)
20 +
0.1CB
300
ns
Fall Time of SDA Signal, Transmitting
tF, TX
(Notes 4, 7)
20 +
0.1CB
250
ns
Pulse Width of Spike Suppressed
tSP
(Notes 4, 8)
50
ns
Capacitive Load for Each Bus Line
CB
(Note 4)
400
pF
Bus Time Out
tTIMEOUT
14
19
27
ms
ESD PROTECTION
ROW7–ROW0, COL7–COL0
IEC 61000-4-2 Air-Gap Discharge
Q
15
kV
IEC 61000-4-2 Contact Discharge
Q
8
All Other Pins
Human Body Model
Q
2.5
kV



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