MAX11331 datasheet(19/37 Pages) MAXIM

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MAX11329–MAX11332

3Msps, 12-/10-Bit, 8-/16-Channel ADCs with

Post-Mux External Signal Conditioning Access

Figure 8. Echo Back the Configuration Data

Alternatively, set SWCNV to 1 in the ADC Mode Control

edge instead of cycling CNVST (Table 2). For proper

operation, CS must be held low for 17 clock cycles to

guarantee that the device interprets the SWCNV setting.

Wait until EOC goes low before pulling CS low to com-

municate with the serial interface. Upon completing the

conversion, SWCNV is reset to 0 (Figure 7).

Analog Input

The MAX11329–MAX11332 produce a digital output that

corresponds to the analog input voltage as long as the

analog inputs are within the specified operating range.

Internal protection diodes confine the analog input volt-

age within the region of the analog power input rails

(VDD, GND) and allow the analog input voltage to swing

from GND - 0.3V to VDD + 0.3V without damaging the

device. Input voltages beyond GND - 0.3V and VDD +

0.3V forward bias the internal protection diodes. Limit the

forward diode current to less than 50mA to avoid dam-

age to the MAX11329–MAX11332.

ECHO

When writing to the ADC Configuration register, set

ECHO to 1 in ADC Configuration register to echo back

the configuration data onto DOUT at time n+1 (Figure 8,

Table 6).

Scan Modes

The MAX11329–MAX11332 feature nine scan modes

(Table 3).

Manual Mode

The next channel to be selected is identified in each SPI

frame. The conversion results are sent out in the next

frame. The manual mode works with the external clock

only. The FIFO is unused.

Repeat Mode

Repeat scanning channel N for number of times and

store all the conversion results in the FIFO. The number of

scans is programmed in the ADC Configuration register.

The repeat mode works with the internal clock only.

Custom_Int and Custom_Ext

In Custom_Int and Custom_Ext modes, the device scans

preprogrammed channels in ascending order. The chan-

nels to be scanned in sequence are programmed in the

Custom Scan0 or Custom Scan1 registers (see Table 12

and Table 13). A new I/P MUX is selected every frame

on the thirteenth falling edge of SCLK. Custom_Int works

with the internal clock. Custom_Ext works with the exter-

nal clock.

Standard_Int and Standard_Ext

In Standard_Int and Standard_Ext modes, the device

scans channels 0 through N in ascending order where

N is the last channel specified in the ADC Mode Control

thirteenth falling edge of SCLK. Standard_Int works with

the internal clock. Standard_Ext works with the external

clock.

Upper_Int and Upper_Ext

In Upper_Int and Upper_Ext modes, the device scans

channels N through 15/11/7/3 in ascending order where

N is the first channel specified in the ADC Mode Control

thirteenth falling edge of SCLK. Upper_Int works with the

internal clock. Upper_Ext works with the external clock.

SampleSet

The SampleSet mode of operation allows the definition

of a unique channel sequence combination with maxi-

mum length of 256. SampleSet is supported only in the

external clock mode. SampleSet is ideally suited for mul-

tichannel measurement applications where some analog

inputs must be converted more often than others.

DIN

t = n-1

DOUT

CONFIGURATION

DATA

CONFIGURATION

DATA

CONFIGURATION

DATA

CONFIGURATION

DATA

CONFIGURATION

DATA

TURN ON ECHO

t = nt = n+1

t = n+2

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